Xilinx manual ML310 PM2 User I/O, RXPPAD21 RXPPAD21AK25

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Chapter 2: ML310 Embedded Development Platform

	Table 2-31:	PM1 Pinout (Continued)

	PM1 Pin	FPGA Pin	Pin Description	ML310 Schematic Net	FPGA Bank
	PM1 Pin	FPGA Pin	Pin Description	ML310 Schematic Net	VCCO
					VCCO
	F17	AK11	RXNPAD18	RXNPAD18_AK11

	F18	AK12	RXPPAD18	RXPPAD18_AK12

	F19	AK24	RXNPAD21	RXNPAD21_AK24

	F20	AK25	RXPPAD21	RXPPAD21_AK25

Notes:

1.LVDS pairs are shown shaded; all other signals are single-ended.

2.LVDS pairs can also be used as single-ended I/O at 2.5V

3.NC indicates a “no connect” signal.

ML310 PM2 User I/O

The PM2 connector makes most of the LVDS pairs available to the user, along with single- ended signals. Table 2-32shows the pinout for the PM2 connector on the ML310.

	Table 2-32:	PM2 Pinout

	PM2 Pin	FPGA Pin		Pin Description	ML310 Schematic Net		FPGA Bank
	PM2 Pin	FPGA Pin		Pin Description	ML310 Schematic Net		VCCO
							VCCO
	A1	T5		IO_L89N_3	PM_IO_69		2.5V

	A2	T6		IO_L89P_3	PM_IO_68		2.5V

	A3	T3		IO_L88N_3	PM_IO_67		2.5V

	A4	T4		IO_L88P_3	PM_IO_66		2.5V

	A5	V3		IO_L58N_3	PM_IO_55		2.5V

	A6	V4		IO_L58P_3	PM_IO_54		2.5V

	A7	U7		IO_L56N_3	PM_IO_51		2.5V

	A8	U8		IO_L56P_3	PM_IO_50		2.5V

	A9	V7		IO_L53N_3	PM_IO_45		2.5V

	A10	V8		IO_L53P_3	PM_IO_44		2.5V

	A11	AC15		IO_L67P_4	PM_IO_72		2.5V

	A12	AB15		IO_L67N_4	PM_IO_73		2.5V

	A13	AA4		IO_L48P_3	PM_IO_34		2.5V

	A14	AA3		IO_L48N_3	PM_IO_35		2.5V

	A15	AD2		IO_L42P_3	PM_IO_22		2.5V

	A16	AD1		IO_L42N_3	PM_IO_23		2.5V

	A17	AG2		IO_L06P_3	PM_IO_6		2.5V

	A18	AG1		IO_L06N_3	PM_IO_7		2.5V

	A19	AH5		IO_L02P_3	PM_IO_0		2.5V

	A20	AG5		IO_L02N_3	PM_IO_1		2.5V


68			www.xilinx.com			ML310 User Guide
			1-800-255-7778			UG068 (v1.01) August 25, 2004

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Contents ML310 User Guide UG068 v1.01 August 25ML310 User Guide ML310 User Guide UG068 v1.01 August 25 Version RevisionUG068 v1.01 August 25 Table of Contents UG068 v1.01 August 25 Manual Contents Additional ResourcesConventions TypographicalOnline Document HandbookChapter Summary of Virtex-II Pro Features Virtex-II ProPowerPC 405 Core RocketIO 3.125 Gb/s TransceiversVirtex-II Fpga Fabric Virtex-II ProFoundation Features Foundation ISEDesign Entry Introduction to Virtex-II Pro, ISE, and EDKFoundation ISE Implementation and ConfigurationSynthesis Embedded Development Kit Board Level IntegrationML310 Embedded Development Platform OverviewML310 Embedded Development Platform ML310 BoardFeatures OverviewBoard Hardware Clock GenerationDDR Memory Board HardwareU37 DDR SignalingDDR Memory Expansion DDRA2 DDRDQS02 DDRDQ31 Signaling Standards of RS-232 Serial Port Fpga UartIntroduction to Serial Ports RS-232 on the ML310System ACE CF Controller Board Bring-UpNon-Volatile Storage XC2VP30 ConnectivityJtag Connection to XC2VP30 6JTAG Connections to the XC2VP30 and System ACEParallel Cable IV Interface System ACE Jtag Configuration InterfaceGpio LEDs and LCD 8LEDs and LCD Connectivity UCF Signal Name Translator U37 J13 U35 Gpio LED InterfaceGpio LCD Interface U37 Name U36Buffer U33 J13 CPU Debug and CPU TraceCPU Debug Description 9Combined Trace/Debug Connector Pinout CPU Debug Connection to XC2VP30 CPU Debug Connector PinoutPCI Bus ML310 Embedded Development Platform 11 PCI Bus and Device Connectivity Pciinta Pciintb Pciintc Pcipar Pcippar Pcirstn Pciprstn ALi South Bridge Interface, M1535D+, U15 113.3V Primary PCI Bus Information Device VendorDevice Name Bus 125.0V Secondary PCI Bus Information Device Name VendorParallel Port Interface, connector assembly P1 12ALi South Bridge Interface, M1535D+, U15Serial Port Interface, connector assembly P1 USB, connector assembly J3 IDE, connectors J15 and J16 17Type of Gpio Available on Header J5 ALi Gpio Types Number GPIO, connector J5System Management Bus SMBus 19Audio Jacks, J1 and J2 Signal name Description AC97 AudioPS/2 Keyboard/Mouse Interface, connector P2 Flash ROM, U4Intel GD82559, U11, 10/100 Ethernet Controller Intel GD82559 Ethernet ControllerIIC/SMBus Signaling IIC/SMBus InterfaceIntroduction to IIC/SMBus IIC/SMBus on ML310 Board22shows the Fpga connections to all SMBus and IIC devices 14SMBus and IIC Block Diagram SPI Signaling Serial Peripheral Interface SPIPush Buttons Push Buttons, Switches, Front Panel Interface and JumpersSPI Addressing System ACE Configuration Dipswitch, SW3 CPU Reset, SW2Front Panel Interface Connector, J23 16SW3 SysACE CFG Switch DetailSYACECFGA0 J10 J11 Coupling JumpersVoltage Jumper ATX Power Distribution and Voltage Regulation MGT Bref Clock Selection Jumpers, J20 and J2117ATX Power Distribution and Voltage Regulation 18Voltage Monitor High-Speed I/O High-Speed I/OML310 PM Connectors 19Personality Module Connected to ML310 BoardPM1 Connector PM2 ConnectorContact Order ML310 PM Utility PinsAdapter Board PM Connectors ML310 PM User I/O Pins PM1 Power and GroundPM2 Power and Ground PM1 User I/ORXPPAD4 RXPPAD4A25 31 PM1 Pinout ML310 PM2 User I/O RXPPAD21 RXPPAD21AK2532 PM2 Pinout AA5