Xilinx ML310 manual GPIO, connector J5, System Management Bus SMBus

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Board Hardware

R

GPIO, connector J5

There are 15 GPIO pins connecting the ALi M1535D+ to the J5 24 pin header. These may be accessed via the ALi M1535D+ via the PCI Bus. Please review the ALi M1535D+ Data sheets for more detailed information.

Table 2-17shows the types and number of GPIO signals available to the user from the ALi South Bridge.

Table 2-17:Type of GPIO Available on Header J5

ALi GPIO Types

Number

Available

 

 

 

Output

5

 

 

Input

4

 

 

Input/Output

6

 

 

Table 2-18shows the connections from the ALi, M1535D+, GPIO signals available at the GPIO header (J5). Please review the ALi M1535D+ Data sheets, located on the ML310 CDROM, for more detailed information.

Table 2-18:GPIO Connections on Header J5

Schem Net Name

GPIO Header

M1535D+

IO Type

(J5)

(U15)

 

 

 

 

 

 

GPO_35

24

P19

Output

 

 

 

 

GPO_34

22

P18

Output

 

 

 

 

GPO_30

20

N18

Output

 

 

 

 

GPO_29

23

N17

Output

 

 

 

 

GPO_10

21

T3

Output

 

 

 

 

GPI_36

7

U8

Input

 

 

 

 

GPI_34

5

W7

Input

 

 

 

 

GPI_25

3

E9

Input

 

 

 

 

GPI_24

1

M17

Input

 

 

 

 

GPIO_3

15

Y4

Input/Output

 

 

 

 

GPIO_23

19

U5

Input/Output

 

 

 

 

GPIO_22

17

U6

Input/Output

 

 

 

 

GPIO_2

13

W4

Input/Output

 

 

 

 

GPIO_1

11

V4

Input/Output

 

 

 

 

GPIO_0

9

Y3

Input/Output

 

 

 

 

System Management Bus (SMBus)

The System Management Bus (SMBus) host controller in the M1535D+ supports the ability to communicate with power related devices using the SMBus protocol. It provides quick

ML310 User Guide

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UG068 (v1.01) August 25, 2004

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Contents UG068 v1.01 August 25 ML310 User GuideML310 User Guide Version Revision ML310 User Guide UG068 v1.01 August 25UG068 v1.01 August 25 Table of Contents UG068 v1.01 August 25 Additional Resources Manual ContentsTypographical ConventionsHandbook Online DocumentChapter Virtex-II Pro Summary of Virtex-II Pro FeaturesRocketIO 3.125 Gb/s Transceivers PowerPC 405 CoreVirtex-II Pro Virtex-II Fpga FabricFoundation ISE Foundation FeaturesDesign Entry Introduction to Virtex-II Pro, ISE, and EDKImplementation and Configuration SynthesisFoundation ISE Board Level Integration Embedded Development KitOverview ML310 Embedded Development PlatformML310 Board ML310 Embedded Development PlatformOverview FeaturesClock Generation Board HardwareBoard Hardware DDR MemoryDDR Signaling DDR Memory ExpansionU37 DDRA2 DDRDQS02 DDRDQ31 Serial Port Fpga Uart Signaling Standards of RS-232Introduction to Serial Ports RS-232 on the ML310Board Bring-Up System ACE CF ControllerXC2VP30 Connectivity Non-Volatile Storage6JTAG Connections to the XC2VP30 and System ACE Jtag Connection to XC2VP30System ACE Jtag Configuration Interface Gpio LEDs and LCDParallel Cable IV Interface 8LEDs and LCD Connectivity Gpio LED Interface UCF Signal Name Translator U37 J13 U35Gpio LCD Interface U37 Name U36CPU Debug and CPU Trace CPU Debug DescriptionBuffer U33 J13 9Combined Trace/Debug Connector Pinout CPU Debug Connector Pinout PCI BusCPU Debug Connection to XC2VP30 ML310 Embedded Development Platform 11 PCI Bus and Device Connectivity Pciinta Pciintb Pciintc Pcipar Pcippar Pcirstn Pciprstn 113.3V Primary PCI Bus Information Device Vendor ALi South Bridge Interface, M1535D+, U15Device Name Bus 125.0V Secondary PCI Bus Information Device Name Vendor12ALi South Bridge Interface, M1535D+, U15 Parallel Port Interface, connector assembly P1Serial Port Interface, connector assembly P1 USB, connector assembly J3 IDE, connectors J15 and J16 GPIO, connector J5 System Management Bus SMBus17Type of Gpio Available on Header J5 ALi Gpio Types Number AC97 Audio 19Audio Jacks, J1 and J2 Signal name DescriptionFlash ROM, U4 PS/2 Keyboard/Mouse Interface, connector P2Intel GD82559 Ethernet Controller Intel GD82559, U11, 10/100 Ethernet ControllerIIC/SMBus Interface IIC/SMBus SignalingIntroduction to IIC/SMBus IIC/SMBus on ML310 Board22shows the Fpga connections to all SMBus and IIC devices 14SMBus and IIC Block Diagram Serial Peripheral Interface SPI SPI SignalingPush Buttons, Switches, Front Panel Interface and Jumpers SPI AddressingPush Buttons CPU Reset, SW2 System ACE Configuration Dipswitch, SW316SW3 SysACE CFG Switch Detail Front Panel Interface Connector, J23SYACECFGA0 Jumpers Voltage JumperJ10 J11 Coupling MGT Bref Clock Selection Jumpers, J20 and J21 ATX Power Distribution and Voltage Regulation17ATX Power Distribution and Voltage Regulation 18Voltage Monitor High-Speed I/O High-Speed I/O19Personality Module Connected to ML310 Board ML310 PM ConnectorsPM2 Connector PM1 ConnectorML310 PM Utility Pins Adapter Board PM ConnectorsContact Order PM1 Power and Ground ML310 PM User I/O PinsPM2 Power and Ground PM1 User I/ORXPPAD4 RXPPAD4A25 31 PM1 Pinout RXPPAD21 RXPPAD21AK25 ML310 PM2 User I/O32 PM2 Pinout AA5