Xilinx ML310 manual 9Combined Trace/Debug Connector Pinout

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Chapter 2: ML310 Embedded Development Platform

The PPC405 JTAG (Joint Test Action Group) Debug port complies with IEEE standard 1149.1-1990, IEEE Standard Test Access Port and Boundary Scan Architecture. This standard describes a method for accessing internal chip resources using a four-signal or five-signal interface. The PPC405 JTAG Debug port supports scan-based board testing and is further enhanced to support the attachment of debug tools. These enhancements comply with the IEEE 1149.1 specifications for vendor-specific extensions and are compatible with standard JTAG hardware for boundary-scan system testing.

The PPC405 JTAG debug port supports the four required JTAG signals: TCK, TMS, TDI, and TDO. It also implements the optional TRST signal. The frequency of the JTAG clock signal can range from 0 MHz (DC) to one-half of the processor clock frequency. The JTAG debug port logic is reset at the same time the system is reset, using TRST. When TRST is asserted, the JTAG TAP controller returns to the test-logic reset state.

Refer to the PPC405 Processor Block Manual for more information on the JTAG debug-port signals. Information on JTAG is found in the IEEE standard 1149.1-1990.(3) (3)

Figure 2-9shows a 38-pin Mictor connector that combines the CPU Trace and the CPU Debug interfaces for high-speed, controlled-impedance signaling. For more information functions: starting and stopping the processor, single-stepping instruction execution on the trace-debug capabilities, how trace-debug works, and how to connect an external trace tool, see the RISCWatch Debugger User’s Guide.

		GND, G1, G2, G3, G4, G5
			MICTOR 38
	TRC_TS6	038	037	ATD_8
		036	035
	TRC_TS5			ATD_9
		034	033
	TRC_TS4			ATD_10
		032	031
	TRC_TS3			ATD_11
		030	029
	TRC_TS2E			ATD_12
		028	027
	TRC_TS1E			ATD_13
		026	025
	TRC_TS2O			ATD_14
		024	023
	TRC_TS1O			ATD_15
		022	021
	ATD 16			CPU_TRST_N
		020	019
	ATD 17			CPU_TDI
2.5V		018	017
	ATD 18			CPU_TMS
		016	015
	ATD 19			CPU_TCK
		014	013
	TRC_VSENSE
		012	011	CPU_TDO
		010	009
		008	007
	TRC_CLK	006	005	CPU_HALT_N
		004	003
		002	001
				UG068_05_20_073004

Figure 2-9:Combined Trace/Debug Connector Pinout

3. Virtex-II Pro Platform FPGA Documentation - Volume 2(a): PPC405 User Manual, March 2002 Release, p. 557.

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	1-800-255-7778	UG068 (v1.01) August 25, 2004