Xilinx ML310 manual Conventions, Typographical

Page 8

 

 

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Chapter :

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Resource

Description/URL

 

 

 

 

 

 

 

 

Problem Solvers

Interactive tools that allow you to troubleshoot your design issues

 

 

 

 

http://support.xilinx.com/support/troubleshoot/psolvers.htm

 

 

 

 

 

 

 

 

Tech Tips

Latest news, design tips, and patch information for the Xilinx

 

 

 

 

design environment

 

 

 

 

http://www.support.xilinx.com/xlnx/xil_tt_home.jsp

 

 

 

 

 

Conventions

This document uses the following conventions. An example illustrates each convention.

Typographical

The following typographical conventions are used in this document:

Convention

 

Meaning or Use

Example

 

 

 

 

 

 

Messages, prompts, and

 

Courier font

 

program files that the system

speed grade: - 100

 

 

displays

 

 

 

 

 

Courier bold

 

Literal commands that you

ngdbuild design_name

 

enter in a syntactical statement

 

 

 

 

 

 

Commands that you select

File Open

Helvetica bold

 

from a menu

 

 

 

 

 

 

 

 

Keyboard shortcuts

Ctrl+C

 

 

 

 

 

 

Variables in a syntax

 

 

 

statement for which you must

ngdbuild design_name

 

 

supply values

 

 

 

 

 

 

 

 

See the Development System

Italic font

 

References to other manuals

Reference Guide for more

 

 

 

information.

 

 

 

 

 

 

 

If a wire is drawn so that it

 

 

Emphasis in text

overlaps the pin of a symbol,

 

 

 

the two nets are not connected.

 

 

 

 

 

 

An optional entry or

 

Square brackets

[ ]

parameter. However, in bus

ngdbuild [option_name]

specifications, such as

design_name

 

 

 

 

bus[7:0], they are required.

 

 

 

 

 

Braces { }

 

A list of items from which you

lowpwr ={onoff}

 

must choose one or more

 

 

 

 

 

 

 

Vertical bar

 

Separates items in a list of

lowpwr ={onoff}

 

choices

 

 

 

 

 

 

 

8

www.xilinx.com

ML310 User Guide

 

1-800-255-7778

UG068 (v1.01) August 25, 2004

Image 8
Contents ML310 User Guide UG068 v1.01 August 25ML310 User Guide ML310 User Guide UG068 v1.01 August 25 Version RevisionUG068 v1.01 August 25 Table of Contents UG068 v1.01 August 25 Manual Contents Additional ResourcesConventions TypographicalOnline Document HandbookChapter Summary of Virtex-II Pro Features Virtex-II ProPowerPC 405 Core RocketIO 3.125 Gb/s TransceiversVirtex-II Fpga Fabric Virtex-II ProFoundation Features Foundation ISEDesign Entry Introduction to Virtex-II Pro, ISE, and EDKFoundation ISE Implementation and ConfigurationSynthesis Embedded Development Kit Board Level IntegrationML310 Embedded Development Platform OverviewML310 Embedded Development Platform ML310 BoardFeatures OverviewBoard Hardware Clock GenerationDDR Memory Board HardwareU37 DDR SignalingDDR Memory Expansion DDRA2 DDRDQS02 DDRDQ31 Signaling Standards of RS-232 Serial Port Fpga UartIntroduction to Serial Ports RS-232 on the ML310System ACE CF Controller Board Bring-UpNon-Volatile Storage XC2VP30 ConnectivityJtag Connection to XC2VP30 6JTAG Connections to the XC2VP30 and System ACEParallel Cable IV Interface System ACE Jtag Configuration InterfaceGpio LEDs and LCD 8LEDs and LCD Connectivity UCF Signal Name Translator U37 J13 U35 Gpio LED InterfaceGpio LCD Interface U37 Name U36Buffer U33 J13 CPU Debug and CPU TraceCPU Debug Description 9Combined Trace/Debug Connector Pinout CPU Debug Connection to XC2VP30 CPU Debug Connector PinoutPCI Bus ML310 Embedded Development Platform 11 PCI Bus and Device Connectivity Pciinta Pciintb Pciintc Pcipar Pcippar Pcirstn Pciprstn ALi South Bridge Interface, M1535D+, U15 113.3V Primary PCI Bus Information Device VendorDevice Name Bus 125.0V Secondary PCI Bus Information Device Name VendorParallel Port Interface, connector assembly P1 12ALi South Bridge Interface, M1535D+, U15Serial Port Interface, connector assembly P1 USB, connector assembly J3 IDE, connectors J15 and J16 17Type of Gpio Available on Header J5 ALi Gpio Types Number GPIO, connector J5System Management Bus SMBus 19Audio Jacks, J1 and J2 Signal name Description AC97 AudioPS/2 Keyboard/Mouse Interface, connector P2 Flash ROM, U4Intel GD82559, U11, 10/100 Ethernet Controller Intel GD82559 Ethernet ControllerIIC/SMBus Signaling IIC/SMBus InterfaceIntroduction to IIC/SMBus IIC/SMBus on ML310 Board22shows the Fpga connections to all SMBus and IIC devices 14SMBus and IIC Block Diagram SPI Signaling Serial Peripheral Interface SPIPush Buttons Push Buttons, Switches, Front Panel Interface and JumpersSPI Addressing System ACE Configuration Dipswitch, SW3 CPU Reset, SW2Front Panel Interface Connector, J23 16SW3 SysACE CFG Switch DetailSYACECFGA0 J10 J11 Coupling JumpersVoltage Jumper ATX Power Distribution and Voltage Regulation MGT Bref Clock Selection Jumpers, J20 and J2117ATX Power Distribution and Voltage Regulation 18Voltage Monitor High-Speed I/O High-Speed I/OML310 PM Connectors 19Personality Module Connected to ML310 BoardPM1 Connector PM2 ConnectorContact Order ML310 PM Utility PinsAdapter Board PM Connectors ML310 PM User I/O Pins PM1 Power and GroundPM2 Power and Ground PM1 User I/ORXPPAD4 RXPPAD4A25 31 PM1 Pinout ML310 PM2 User I/O RXPPAD21 RXPPAD21AK2532 PM2 Pinout AA5