Xilinx ML310 manual PCI Bus and Device Connectivity

Page 37

Board Hardware

R

		3.3V	PCI-to-PCI
		3.3V	Bridge TI2250 5.0V
			U32			5.0V PCI Slot 6
					PCI_S_CLK0	5.0V PCI Slot 6
					PCI_S_CLK0
					PCI_S_AD18 IDSEL
						PCI_BUS
					PCI_S_CLK1	5.0V PCI Slot 4
					PCI_S_CLK1
U37			0xAC23 104C		PCI_S_AD19	IDSEL
	PCI_P_AD24	PCI_P_AD25	0xAC23 104C		PCI_S_AD19	IDSEL
IDSEL	PCI_P_AD24	PCI_P_AD25	IDSEL			PCI_BUS
IDSEL
PCI Bus
PCI Bus			PCI_BUS
Virtex-II Pro	PCI_P_CLK5
Virtex-II Pro	PCI_P_CLK4					3.3V PCI Slot 5
FPGA	PCI_P_CLK4					3.3V PCI Slot 5
FPGA	PCI_P_CLK0
XC2VP30	PCI_P_CLK1				PCI_P_AD21	IDSEL
	PCI_P_CLK2				PCI_P_AD21	IDSEL
	PCI_P_CLK2					PCI_BUS
	PCI_P_CLK3					PCI_BUS
	PCI_P_CLK3					3.3V PCI Slot 3
						3.3V PCI Slot 3
					PCI_P_AD22 IDSEL
						PCI_BUS
				Intel 10/100
				Ethernet NIC
					U11
		PCI_P_AD23 IDSEL			0x1229 8086
			PCI_BUS
			ALi Southbridge
				U15
		PCI_P_AD17	IDSEL	Dev ID Vend ID
		PCI_P_AD17	Audio	0x5451 10B9
		PCI_P_AD18	Audio	0x5451 10B9
		PCI_P_AD18	S. Bridge 0x1533 10B9
		PCI_P_AD19	S. Bridge 0x1533 10B9
		PCI_P_AD19	Modem	0x5457 10B9
		PCI_P_AD26	Modem	0x5457 10B9
		PCI_P_AD26	USB#2	0x5237 10B9
		PCI_P_AD27	USB#2	0x5237 10B9
		PCI_P_AD27	IDE Bus	0x5229 10B9
		PCI_P_AD31	IDE Bus	0x5229 10B9
		PCI_P_AD31	USB#1	0x5237 10B9
			USB#1	0x5237 10B9
			PCI_BUS
	Figure 2-11:PCI Bus and Device Connectivity

Table 2-10shows the connections for the PCI controller.

Table 2-10:PCI Controller Connections

UCF Signal Name	XC2VP30 Pin (U37)	Description

PCI_CLK0	T2	PCI_P_CLK0

PCI_CLK1	R2	PCI_P_CLK1

PCI_CLK2	R5	PCI_P_CLK2

PCI_CLK3	R6	PCI_P_CLK3

PCI_CLK4	R3	PCI_P_CLK4

PCI_CLK5	R4	PCI_P_CLK5

PCI_CLK5_FB	C15	PCI_P_CLK5

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UG068 (v1.01) August 25, 2004	1-800-255-7778

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Contents UG068 v1.01 August 25 ML310 User GuideML310 User Guide Version Revision ML310 User Guide UG068 v1.01 August 25UG068 v1.01 August 25 Table of Contents UG068 v1.01 August 25 Additional Resources Manual ContentsTypographical ConventionsHandbook Online DocumentChapter Virtex-II Pro Summary of Virtex-II Pro FeaturesRocketIO 3.125 Gb/s Transceivers PowerPC 405 CoreVirtex-II Pro Virtex-II Fpga FabricFoundation ISE Foundation FeaturesDesign Entry Introduction to Virtex-II Pro, ISE, and EDKSynthesis Implementation and ConfigurationFoundation ISE Board Level Integration Embedded Development KitOverview ML310 Embedded Development PlatformML310 Board ML310 Embedded Development PlatformOverview FeaturesClock Generation Board HardwareBoard Hardware DDR MemoryDDR Memory Expansion DDR SignalingU37 DDRA2 DDRDQS02 DDRDQ31 Serial Port Fpga Uart Signaling Standards of RS-232Introduction to Serial Ports RS-232 on the ML310Board Bring-Up System ACE CF ControllerXC2VP30 Connectivity Non-Volatile Storage6JTAG Connections to the XC2VP30 and System ACE Jtag Connection to XC2VP30Gpio LEDs and LCD System ACE Jtag Configuration InterfaceParallel Cable IV Interface 8LEDs and LCD Connectivity Gpio LED Interface UCF Signal Name Translator U37 J13 U35Gpio LCD Interface U37 Name U36CPU Debug Description CPU Debug and CPU TraceBuffer U33 J13 9Combined Trace/Debug Connector Pinout PCI Bus CPU Debug Connector PinoutCPU Debug Connection to XC2VP30 ML310 Embedded Development Platform 11 PCI Bus and Device Connectivity Pciinta Pciintb Pciintc Pcipar Pcippar Pcirstn Pciprstn 113.3V Primary PCI Bus Information Device Vendor ALi South Bridge Interface, M1535D+, U15Device Name Bus 125.0V Secondary PCI Bus Information Device Name Vendor12ALi South Bridge Interface, M1535D+, U15 Parallel Port Interface, connector assembly P1Serial Port Interface, connector assembly P1 USB, connector assembly J3 IDE, connectors J15 and J16 System Management Bus SMBus GPIO, connector J517Type of Gpio Available on Header J5 ALi Gpio Types Number AC97 Audio 19Audio Jacks, J1 and J2 Signal name DescriptionFlash ROM, U4 PS/2 Keyboard/Mouse Interface, connector P2Intel GD82559 Ethernet Controller Intel GD82559, U11, 10/100 Ethernet ControllerIIC/SMBus Interface IIC/SMBus SignalingIntroduction to IIC/SMBus IIC/SMBus on ML310 Board22shows the Fpga connections to all SMBus and IIC devices 14SMBus and IIC Block Diagram Serial Peripheral Interface SPI SPI SignalingSPI Addressing Push Buttons, Switches, Front Panel Interface and JumpersPush Buttons CPU Reset, SW2 System ACE Configuration Dipswitch, SW316SW3 SysACE CFG Switch Detail Front Panel Interface Connector, J23SYACECFGA0 Voltage Jumper JumpersJ10 J11 Coupling MGT Bref Clock Selection Jumpers, J20 and J21 ATX Power Distribution and Voltage Regulation17ATX Power Distribution and Voltage Regulation 18Voltage Monitor High-Speed I/O High-Speed I/O19Personality Module Connected to ML310 Board ML310 PM ConnectorsPM2 Connector PM1 ConnectorAdapter Board PM Connectors ML310 PM Utility PinsContact Order PM1 Power and Ground ML310 PM User I/O PinsPM2 Power and Ground PM1 User I/ORXPPAD4 RXPPAD4A25 31 PM1 Pinout RXPPAD21 RXPPAD21AK25 ML310 PM2 User I/O32 PM2 Pinout AA5