Xilinx ML310 manual Jumpers, Voltage Jumper, J10 J11 Coupling

Page 57

Board Hardware

Table 2-25:Front Panel Interface connector, J23

R

J23

Schem Signal

Description

Pin

 

 

 

 

 

15

KBINH

Tie this pin to GND to activate Keyboard inhibit, see

 

 

ALi M1536D+ data sheet for more details

 

 

 

16

VCC5V

5V ATX power available to user

 

 

 

17

ATX_IDELED_R

ATX IDE access indicator, Tie this pin to Anode of

 

 

user’s LED and Cathode to GND

 

 

 

18

VCC5V

5V ATX power available to user

 

 

 

19

PWR_SUPPLY_ON

Short this pin to GND to enable the ATX power

 

 

supply. Note: This pin cannot be controlled by a

 

 

momentary pulse.

 

 

 

20

GND

Ground

 

 

 

21

PB_SYSACE_RESET

Used to reset System ACE when driven low, as

 

 

described earlier, “System ACE Reset, SW1”

 

 

 

22

GND

Ground

 

 

 

23

PB_FPGA_CPU_RESET

Used to reset CPU when driven low, as described

 

 

earlier, “CPU Reset, SW2”

 

 

 

24

GND

Ground

 

 

 

Jumpers

MGT VTRX Termination Voltage Jumpers, J10 and J11

The MGT receive termination voltage, VTRX, on the top and bottom MGTs are jumper selectable via jumpers J10 (top) and J11 (bottom). The onboard regulated VTRX termination voltage can be configured for AC or DC coupling, 1.8V or 2.5V respectively.

Table 2-26shows the MGT VTRX voltage selections available on the ML310 board.

Table 2-26:Jumper Selection for Top and Bottom MGT VTRX Voltages,J10/J11

MGTs

VTRX

Voltage

Jumper

Jumper

MGT RX

(J10)

(J11)

Coupling

 

 

 

 

 

 

 

 

 

All Top

MGT_VTT

1.8V

Shunt 2 - 3

Open

AC

 

 

 

 

 

 

 

MGT_AVCC

2.5V

Shunt 1 - 2

Open

DC

 

 

 

 

 

 

All Bottom

MGT_VTT

1.8V

Open

Shunt 2 - 3

AC

 

 

 

 

 

 

 

MGT_AVCC

2.5V

Open

Shunt 1- 2

DC

 

 

 

 

 

 

All

MGT_VTT

1.8V

Open

Open

Default

 

 

 

 

 

 

 

MGT_AVCC

2.5V

Open

Open

Default

 

 

 

 

 

 

ML310 User Guide

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UG068 (v1.01) August 25, 2004

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Image 57
Contents UG068 v1.01 August 25 ML310 User GuideML310 User Guide Version Revision ML310 User Guide UG068 v1.01 August 25UG068 v1.01 August 25 Table of Contents UG068 v1.01 August 25 Additional Resources Manual ContentsTypographical ConventionsHandbook Online DocumentChapter Virtex-II Pro Summary of Virtex-II Pro FeaturesRocketIO 3.125 Gb/s Transceivers PowerPC 405 CoreVirtex-II Pro Virtex-II Fpga FabricFoundation ISE Foundation FeaturesDesign Entry Introduction to Virtex-II Pro, ISE, and EDKImplementation and Configuration SynthesisFoundation ISE Board Level Integration Embedded Development KitOverview ML310 Embedded Development PlatformML310 Board ML310 Embedded Development PlatformOverview FeaturesClock Generation Board HardwareBoard Hardware DDR MemoryDDR Signaling DDR Memory ExpansionU37 DDRA2 DDRDQS02 DDRDQ31 Serial Port Fpga Uart Signaling Standards of RS-232Introduction to Serial Ports RS-232 on the ML310Board Bring-Up System ACE CF ControllerXC2VP30 Connectivity Non-Volatile Storage6JTAG Connections to the XC2VP30 and System ACE Jtag Connection to XC2VP30System ACE Jtag Configuration Interface Gpio LEDs and LCDParallel Cable IV Interface 8LEDs and LCD Connectivity Gpio LED Interface UCF Signal Name Translator U37 J13 U35Gpio LCD Interface U37 Name U36CPU Debug and CPU Trace CPU Debug DescriptionBuffer U33 J13 9Combined Trace/Debug Connector Pinout CPU Debug Connector Pinout PCI BusCPU Debug Connection to XC2VP30 ML310 Embedded Development Platform 11 PCI Bus and Device Connectivity Pciinta Pciintb Pciintc Pcipar Pcippar Pcirstn Pciprstn 113.3V Primary PCI Bus Information Device Vendor ALi South Bridge Interface, M1535D+, U15Device Name Bus 125.0V Secondary PCI Bus Information Device Name Vendor12ALi South Bridge Interface, M1535D+, U15 Parallel Port Interface, connector assembly P1Serial Port Interface, connector assembly P1 USB, connector assembly J3 IDE, connectors J15 and J16 GPIO, connector J5 System Management Bus SMBus17Type of Gpio Available on Header J5 ALi Gpio Types Number AC97 Audio 19Audio Jacks, J1 and J2 Signal name DescriptionFlash ROM, U4 PS/2 Keyboard/Mouse Interface, connector P2Intel GD82559 Ethernet Controller Intel GD82559, U11, 10/100 Ethernet ControllerIIC/SMBus Interface IIC/SMBus SignalingIntroduction to IIC/SMBus IIC/SMBus on ML310 Board22shows the Fpga connections to all SMBus and IIC devices 14SMBus and IIC Block Diagram Serial Peripheral Interface SPI SPI SignalingPush Buttons, Switches, Front Panel Interface and Jumpers SPI AddressingPush Buttons CPU Reset, SW2 System ACE Configuration Dipswitch, SW316SW3 SysACE CFG Switch Detail Front Panel Interface Connector, J23SYACECFGA0 Jumpers Voltage JumperJ10 J11 Coupling MGT Bref Clock Selection Jumpers, J20 and J21 ATX Power Distribution and Voltage Regulation17ATX Power Distribution and Voltage Regulation 18Voltage Monitor High-Speed I/O High-Speed I/O19Personality Module Connected to ML310 Board ML310 PM ConnectorsPM2 Connector PM1 ConnectorML310 PM Utility Pins Adapter Board PM ConnectorsContact Order PM1 Power and Ground ML310 PM User I/O PinsPM2 Power and Ground PM1 User I/ORXPPAD4 RXPPAD4A25 31 PM1 Pinout RXPPAD21 RXPPAD21AK25 ML310 PM2 User I/O32 PM2 Pinout AA5