Xilinx ML310 manual ATX Power Distribution and Voltage Regulation

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Chapter 2: ML310 Embedded Development Platform

MGT BREF Clock Selection Jumpers, J20 and J21

One of two onboard LVDS BREF clock sources, X7 or X9, can be selected via jumpers, J20 and J21. The selected clock source drives both top and bottom LVDS BREF Clock input pairs to the XC2VP30 FPGA.

Table 2-27shows the MGT BREF clock selections available on the ML310 board.

Table 2-27:Jumper Selection for MGT BREF clocks,J20/J21

BREF Clock Freq.

Jumper

Jumper

Description

(J10)

(J11)

 

 

 

 

 

 

156.25MHz

Shunt 1 - 2

Shunt 1 - 2

LVDS Oscillator, X7, 156.25MHz

 

 

 

 

125.00MHz

Shunt 2 - 3

Shunt 2 - 3

LVDS Oscillator, X9, 125.00MHz

 

 

 

 

Note: BREF Clock Pins driven on the XC2VP30 FPGA are:

LVDS_CLKLOC_P (U37-F16/AH16)

LVDS_CLKLOC_N (U37-G16/AJ16)

System ACE Configuration Mode Jumper, J14

Selects the System ACE configuration mode behavior after reset or power up.

J14 = Open (default)

Allows System ACE CF to configure immediately after reset or power up J14 = Shorted

Inhibits the System ACE from configuring after reset or power up and can only be commanded by the MPU control to do so. Please review section “System ACE CF Controller” and the System ACE data sheet for more details on the System ACE device operation, which can be found on the ML310 CDROM

JTAG Source Select Jumper, J19

The JTAG Source Select jumper (J19) enables the use of either the Parallel Cable IV connector (J9) or the CPU_DEBUG/Trace Port connectors, J12/P8, to source the XC2VP30 JTAG pins. This is available for third party tool support. The muxing is performed by an external device, 74LVC157A (U39), as shown earlier in Figure 2-6. The data sheet for this device is available on the ML310 CDROM.

Note: This functionality should not be used if the user implements logic that also drives the CPU DEBUG connector (J12) as contention may result after the FPGA is configured.

J19 = Open (default, use the Parallel Cable IV connector, J9)

ATX Power Distribution and Voltage Regulation

The ML310 board is shipped with a commercially available 250W ATX Power supply. All voltages required by the ML310 logic devices are derived from the 5.0V supply, except the +/- 12V supplies, as shown in Figure 2-17. The ML310 ATX power supply can easily be mounted in a standard ATX Chassis along with the ML310 board.

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ML310 User Guide

 

1-800-255-7778

UG068 (v1.01) August 25, 2004

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Contents ML310 User Guide UG068 v1.01 August 25ML310 User Guide ML310 User Guide UG068 v1.01 August 25 Version RevisionUG068 v1.01 August 25 Table of Contents UG068 v1.01 August 25 Manual Contents Additional ResourcesConventions TypographicalOnline Document HandbookChapter Summary of Virtex-II Pro Features Virtex-II ProPowerPC 405 Core RocketIO 3.125 Gb/s TransceiversVirtex-II Fpga Fabric Virtex-II ProDesign Entry Foundation FeaturesFoundation ISE Introduction to Virtex-II Pro, ISE, and EDKSynthesis Implementation and ConfigurationFoundation ISE Embedded Development Kit Board Level IntegrationML310 Embedded Development Platform OverviewML310 Embedded Development Platform ML310 BoardFeatures OverviewBoard Hardware Clock GenerationDDR Memory Board HardwareDDR Memory Expansion DDR SignalingU37 DDRA2 DDRDQS02 DDRDQ31 Introduction to Serial Ports Signaling Standards of RS-232Serial Port Fpga Uart RS-232 on the ML310System ACE CF Controller Board Bring-UpNon-Volatile Storage XC2VP30 ConnectivityJtag Connection to XC2VP30 6JTAG Connections to the XC2VP30 and System ACEGpio LEDs and LCD System ACE Jtag Configuration InterfaceParallel Cable IV Interface 8LEDs and LCD Connectivity Gpio LCD Interface UCF Signal Name Translator U37 J13 U35Gpio LED Interface U37 Name U36CPU Debug Description CPU Debug and CPU TraceBuffer U33 J13 9Combined Trace/Debug Connector Pinout PCI Bus CPU Debug Connector PinoutCPU Debug Connection to XC2VP30 ML310 Embedded Development Platform 11 PCI Bus and Device Connectivity Pciinta Pciintb Pciintc Pcipar Pcippar Pcirstn Pciprstn Device Name Bus ALi South Bridge Interface, M1535D+, U15113.3V Primary PCI Bus Information Device Vendor 125.0V Secondary PCI Bus Information Device Name VendorParallel Port Interface, connector assembly P1 12ALi South Bridge Interface, M1535D+, U15Serial Port Interface, connector assembly P1 USB, connector assembly J3 IDE, connectors J15 and J16 System Management Bus SMBus GPIO, connector J517Type of Gpio Available on Header J5 ALi Gpio Types Number 19Audio Jacks, J1 and J2 Signal name Description AC97 AudioPS/2 Keyboard/Mouse Interface, connector P2 Flash ROM, U4Intel GD82559, U11, 10/100 Ethernet Controller Intel GD82559 Ethernet ControllerIntroduction to IIC/SMBus IIC/SMBus SignalingIIC/SMBus Interface IIC/SMBus on ML310 Board22shows the Fpga connections to all SMBus and IIC devices 14SMBus and IIC Block Diagram SPI Signaling Serial Peripheral Interface SPISPI Addressing Push Buttons, Switches, Front Panel Interface and JumpersPush Buttons System ACE Configuration Dipswitch, SW3 CPU Reset, SW2Front Panel Interface Connector, J23 16SW3 SysACE CFG Switch DetailSYACECFGA0 Voltage Jumper JumpersJ10 J11 Coupling ATX Power Distribution and Voltage Regulation MGT Bref Clock Selection Jumpers, J20 and J2117ATX Power Distribution and Voltage Regulation 18Voltage Monitor High-Speed I/O High-Speed I/OML310 PM Connectors 19Personality Module Connected to ML310 BoardPM1 Connector PM2 ConnectorAdapter Board PM Connectors ML310 PM Utility PinsContact Order PM2 Power and Ground ML310 PM User I/O PinsPM1 Power and Ground PM1 User I/ORXPPAD4 RXPPAD4A25 31 PM1 Pinout ML310 PM2 User I/O RXPPAD21 RXPPAD21AK2532 PM2 Pinout AA5