Xilinx ML310 manual Push Buttons, Switches, Front Panel Interface and Jumpers, SPI Addressing

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Board Hardware

R

SPI Addressing

The SPI does not use an addressed based system like the IIC Bus Interface uses. Instead, devices are selected by dedicated Slave Select signals, comparable to a Chip Select signal. Each SPI Slave device needs its own Slave Select signal driven from the SPI master. This increases the total pin count, but decreases overhead and complexity, which increases the available bandwidth and decreases bus contention.

The ML310 employs a single SPI device which is a 25LC640, 64k bits EEPROM. For more details on this device, please review the data sheet available on the ML310 CDROM.

Table 2-15shows the FPGA and the EEPROM connected by the SPI bus.

U37

Virtex-II Pro

FPGA

XC2VP30

SPI Bus

U19

 

SPI

EEPROM

25LC640

Figure 2-15:SPI EEPROM Device Interface

Table 2-24shows the connections between the SMBus/IIC controller. and the XC2VP30.

Table 2-24:SMBus and IIC Controller Connections

UCF Signal Name

XC2VP30 Pin (U37)

Schem Signal Name

 

 

 

spi_miso

AJ10

SPI_DATA_OUT

 

 

 

spi_mosi

AK10

SPI_DATA_IN

 

 

 

spi_sck

AF12

SPI_CLK

 

 

 

spi_ss[0]

AF13

SPI_DATA_CS_N

 

 

 

*Note: This signal connects to U20 therm_l on the LM87. See data sheet for additional details.

Push Buttons, Switches, Front Panel Interface and Jumpers

Push Buttons

System ACE Reset, SW1

SW1 provides a way to manually reset the System ACE CF (U38) device. When SW1 is actuated it drives the signal PB_SYSTEM_ACE_RESET low which causes the LTC1326 (U31) to generate a 100us active low pulse. The active low output of the LTC1326 drives the reset input of the System ACE CF (U38) device via signal SYSTEMACE_RESET_N.

When the System ACE CF device is reset, it causes a re-configuration of the XC2VP30 FPGA. The ace file used to program the device is selected via dipswitch, SW3, settings. Please review the System ACE CF data sheet for more details, as it is located on the ML310 CDROM and also available on http://www.xilinx.com

The front panel interface header (J23) can also drive the PB_SYSTEM_ACE_RESET signal. For more details on J23, please review section “Front Panel Interface Connector, J23”.

ML310 User Guide

www.xilinx.com

53

UG068 (v1.01) August 25, 2004

1-800-255-7778

 

Image 53
Contents UG068 v1.01 August 25 ML310 User GuideML310 User Guide Version Revision ML310 User Guide UG068 v1.01 August 25UG068 v1.01 August 25 Table of Contents UG068 v1.01 August 25 Additional Resources Manual ContentsTypographical ConventionsHandbook Online DocumentChapter Virtex-II Pro Summary of Virtex-II Pro FeaturesRocketIO 3.125 Gb/s Transceivers PowerPC 405 CoreVirtex-II Pro Virtex-II Fpga FabricFoundation ISE Foundation FeaturesDesign Entry Introduction to Virtex-II Pro, ISE, and EDKFoundation ISE Implementation and ConfigurationSynthesis Board Level Integration Embedded Development KitOverview ML310 Embedded Development PlatformML310 Board ML310 Embedded Development PlatformOverview FeaturesClock Generation Board HardwareBoard Hardware DDR MemoryU37 DDR SignalingDDR Memory Expansion DDRA2 DDRDQS02 DDRDQ31 Serial Port Fpga Uart Signaling Standards of RS-232Introduction to Serial Ports RS-232 on the ML310Board Bring-Up System ACE CF ControllerXC2VP30 Connectivity Non-Volatile Storage6JTAG Connections to the XC2VP30 and System ACE Jtag Connection to XC2VP30Parallel Cable IV Interface System ACE Jtag Configuration InterfaceGpio LEDs and LCD 8LEDs and LCD Connectivity Gpio LED Interface UCF Signal Name Translator U37 J13 U35Gpio LCD Interface U37 Name U36Buffer U33 J13 CPU Debug and CPU TraceCPU Debug Description 9Combined Trace/Debug Connector Pinout CPU Debug Connection to XC2VP30 CPU Debug Connector PinoutPCI Bus ML310 Embedded Development Platform 11 PCI Bus and Device Connectivity Pciinta Pciintb Pciintc Pcipar Pcippar Pcirstn Pciprstn 113.3V Primary PCI Bus Information Device Vendor ALi South Bridge Interface, M1535D+, U15Device Name Bus 125.0V Secondary PCI Bus Information Device Name Vendor12ALi South Bridge Interface, M1535D+, U15 Parallel Port Interface, connector assembly P1Serial Port Interface, connector assembly P1 USB, connector assembly J3 IDE, connectors J15 and J16 17Type of Gpio Available on Header J5 ALi Gpio Types Number GPIO, connector J5System Management Bus SMBus AC97 Audio 19Audio Jacks, J1 and J2 Signal name DescriptionFlash ROM, U4 PS/2 Keyboard/Mouse Interface, connector P2Intel GD82559 Ethernet Controller Intel GD82559, U11, 10/100 Ethernet ControllerIIC/SMBus Interface IIC/SMBus SignalingIntroduction to IIC/SMBus IIC/SMBus on ML310 Board22shows the Fpga connections to all SMBus and IIC devices 14SMBus and IIC Block Diagram Serial Peripheral Interface SPI SPI SignalingPush Buttons Push Buttons, Switches, Front Panel Interface and JumpersSPI Addressing CPU Reset, SW2 System ACE Configuration Dipswitch, SW316SW3 SysACE CFG Switch Detail Front Panel Interface Connector, J23SYACECFGA0 J10 J11 Coupling JumpersVoltage Jumper MGT Bref Clock Selection Jumpers, J20 and J21 ATX Power Distribution and Voltage Regulation17ATX Power Distribution and Voltage Regulation 18Voltage Monitor High-Speed I/O High-Speed I/O19Personality Module Connected to ML310 Board ML310 PM ConnectorsPM2 Connector PM1 ConnectorContact Order ML310 PM Utility PinsAdapter Board PM Connectors PM1 Power and Ground ML310 PM User I/O PinsPM2 Power and Ground PM1 User I/ORXPPAD4 RXPPAD4A25 31 PM1 Pinout RXPPAD21 RXPPAD21AK25 ML310 PM2 User I/O32 PM2 Pinout AA5