Xilinx ML310 manual Features, Overview

Page 19

Overview

R

Figure 2-2shows a high-level block diagram of the ML310 and its peripherals.

CF System ACE

SysACE

INTC

OPB

Bus

PLB BRAM

 

OPB2PLB

 

Bridge

DDR

PLB

Bus

 

256MB

DDR DIMM

RS232

SMBus

SPI

GPIO / LEDs

GPIO SPI SMBus UART

PCI Bridge

PLB2OPB

Bridge

PPC

405

OCM

Bus

OCM BRAM

XC2VP30

FF896

8 RocketIO MGTs 3 LVDS pairs 1 LVDS Clock pair

38 Single-EndedI/O

 

 

 

 

39 LVDS Pairs

1 Clock

High-Speed

PM1

High-Speed

PM2

3.3V PCI

RJ45

 

 

 

Intel GD82559

 

TI

 

 

 

10/100 Ethernet NIC

 

PCI 2250

 

 

 

 

 

 

 

 

 

 

 

 

5V PCI

5V PCI

Slots

3.3V PCI

Slots

AMD

 

 

 

 

 

 

 

 

 

 

 

RS232

 

 

 

 

 

 

 

 

 

 

 

Flash

 

 

 

 

 

 

 

 

 

 

 

(2)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GPIO

 

 

 

 

ALi

 

 

 

 

PS/2

 

 

 

 

 

 

 

 

K/M

 

 

 

 

 

 

 

 

 

 

M1535D+

 

 

 

 

 

 

 

IDE

 

 

 

Parallel

 

 

 

South Bridge

 

 

 

 

(2)

 

 

 

 

 

 

 

Port

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

USB

 

 

 

 

 

 

 

 

 

 

 

SMBus

(2)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Audio

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 2-2:ML310 High-Level Block Diagram

Features

In addition to the Virtex-II Pro™ FPGA with the embedded PPC405, the ML310 board features the following:

•ATX Motherboard formfactor

•256 MB DDR DIMM

•System ACE™ CF Controller

•512 MB CompactFlash card

•Onboard 10/100 Ethernet NIC

•4 PCI slots (3.3V and 5V)

•LCD character display and cable

•FPGA serial port connection

•RS-232 mini-cable

•Personality module interface for RocketIO and LVDS access

•Standard JTAG connectivity

•ALi Super I/O

♦ 1 parallel and 2 serial ports

ML310 User Guide

www.xilinx.com

19

UG068 (v1.01) August 25, 2004

1-800-255-7778

 

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Page 18 Page 20
Contents UG068 v1.01 August 25 ML310 User GuideML310 User Guide Version Revision ML310 User Guide UG068 v1.01 August 25UG068 v1.01 August 25 Table of Contents UG068 v1.01 August 25 Additional Resources Manual ContentsTypographical ConventionsHandbook Online DocumentChapter Virtex-II Pro Summary of Virtex-II Pro FeaturesRocketIO 3.125 Gb/s Transceivers PowerPC 405 CoreVirtex-II Pro Virtex-II Fpga FabricIntroduction to Virtex-II Pro, ISE, and EDK Foundation FeaturesFoundation ISE Design EntrySynthesis Implementation and ConfigurationFoundation ISE Board Level Integration Embedded Development KitOverview ML310 Embedded Development PlatformML310 Board ML310 Embedded Development PlatformOverview FeaturesClock Generation Board HardwareBoard Hardware DDR MemoryDDR Memory Expansion DDR SignalingU37 DDRA2 DDRDQS02 DDRDQ31 RS-232 on the ML310 Signaling Standards of RS-232Serial Port Fpga Uart Introduction to Serial PortsBoard Bring-Up System ACE CF ControllerXC2VP30 Connectivity Non-Volatile Storage6JTAG Connections to the XC2VP30 and System ACE Jtag Connection to XC2VP30Gpio LEDs and LCD System ACE Jtag Configuration InterfaceParallel Cable IV Interface 8LEDs and LCD Connectivity U37 Name U36 UCF Signal Name Translator U37 J13 U35Gpio LED Interface Gpio LCD InterfaceCPU Debug Description CPU Debug and CPU TraceBuffer U33 J13 9Combined Trace/Debug Connector Pinout PCI Bus CPU Debug Connector PinoutCPU Debug Connection to XC2VP30 ML310 Embedded Development Platform 11 PCI Bus and Device Connectivity Pciinta Pciintb Pciintc Pcipar Pcippar Pcirstn Pciprstn 125.0V Secondary PCI Bus Information Device Name Vendor ALi South Bridge Interface, M1535D+, U15113.3V Primary PCI Bus Information Device Vendor Device Name Bus12ALi South Bridge Interface, M1535D+, U15 Parallel Port Interface, connector assembly P1Serial Port Interface, connector assembly P1 USB, connector assembly J3 IDE, connectors J15 and J16 System Management Bus SMBus GPIO, connector J517Type of Gpio Available on Header J5 ALi Gpio Types Number AC97 Audio 19Audio Jacks, J1 and J2 Signal name DescriptionFlash ROM, U4 PS/2 Keyboard/Mouse Interface, connector P2Intel GD82559 Ethernet Controller Intel GD82559, U11, 10/100 Ethernet ControllerIIC/SMBus on ML310 Board IIC/SMBus SignalingIIC/SMBus Interface Introduction to IIC/SMBus22shows the Fpga connections to all SMBus and IIC devices 14SMBus and IIC Block Diagram Serial Peripheral Interface SPI SPI SignalingSPI Addressing Push Buttons, Switches, Front Panel Interface and JumpersPush Buttons CPU Reset, SW2 System ACE Configuration Dipswitch, SW316SW3 SysACE CFG Switch Detail Front Panel Interface Connector, J23SYACECFGA0 Voltage Jumper JumpersJ10 J11 Coupling MGT Bref Clock Selection Jumpers, J20 and J21 ATX Power Distribution and Voltage Regulation17ATX Power Distribution and Voltage Regulation 18Voltage Monitor High-Speed I/O High-Speed I/O19Personality Module Connected to ML310 Board ML310 PM ConnectorsPM2 Connector PM1 ConnectorAdapter Board PM Connectors ML310 PM Utility PinsContact Order PM1 User I/O ML310 PM User I/O PinsPM1 Power and Ground PM2 Power and GroundRXPPAD4 RXPPAD4A25 31 PM1 Pinout RXPPAD21 RXPPAD21AK25 ML310 PM2 User I/O32 PM2 Pinout AA5
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