Xilinx ML310 manual 32 PM2 Pinout

Page 69

High-Speed I/O

Table 2-32: PM2 Pinout (Continued)

R

PM2 Pin

FPGA Pin

Pin Description

ML310 Schematic Net

FPGA Bank

VCCO

 

 

 

 

C1

W1

IO_L57N_3

PM_IO_53

2.5V

 

 

 

 

 

C2

Y1

IO_L57P_3

PM_IO_52

2.5V

 

 

 

 

 

C3

U4

IO_L85N_3

PM_IO_61

2.5V

 

 

 

 

 

C4

U5

IO_L85P_3

PM_IO_60

2.5V

 

 

 

 

 

C5

W5

IO_L50N_3

PM_IO_39

2.5V

 

 

 

 

 

C6

W6

IO_L50P_3

PM_IO_38

2.5V

 

 

 

 

 

C7

V5

IO_L55N_3

PM_IO_49

2.5V

 

 

 

 

 

C8

V6

IO_L55P_3

PM_IO_48

2.5V

 

 

 

 

 

C9

AE14

IO_L68P_4

PM_IO_74

2.5V

 

 

 

 

 

C10

AD14

IO_L68N_4

PM_IO_75

2.5V

 

 

 

 

 

C11

AB6

IO_L40P_3

PM_IO_20

2.5V

 

 

 

 

 

C12

AB5

IO_L40N_3

PM_IO_21

2.5V

 

 

 

 

 

C13

AC2

IO_L45P_3

PM_IO_28

2.5V

 

 

 

 

 

C14

AB2

IO_L45N_3

PM_IO_29

2.5V

 

 

 

 

 

C15

AD2

IO_L42P_3

PM_IO_14

2.5V

 

 

 

 

 

C16

AD1

IO_L42N_3

PM_IO_15

2.5V

 

 

 

 

 

C17

AH4

IO_L04P_3

PM_IO_4

2.5V

 

 

 

 

 

C18

AG3

IO_L04N_3

PM_IO_5

2.5V

 

 

 

 

 

C19

AF6

IO_L31P_3

PM_IO_8

2.5V

 

 

 

 

 

C20

AE5

IO_L31N_3

PM_IO_9

2.5V

 

 

 

 

 

D1

U1

IO_L90N_3

PM_IO_71

2.5V

 

 

 

 

 

D2

V1

IO_L90P_3

PM_IO_70

2.5V

 

 

 

 

 

D3

T7

IO_L86N_3

PM_IO_63

2.5V

 

 

 

 

 

D4

T8

IO_L86P_3

PM_IO_62

2.5V

 

 

 

 

 

D5

V2

IO_L60N_3

PM_IO_59

2.5V

 

 

 

 

 

D6

W2

IO_L60P_3

PM_IO_58

2.5V

 

 

 

 

 

D7

W3

IO_L52N_3

PM_IO_43

2.5V

 

 

 

 

 

D8

W4

IO_L52P_3

PM_IO_42

2.5V

 

 

 

 

 

D9

T9

IO_L59N_3

PM_IO_57

2.5V

 

 

 

 

 

D10

U9

IO_L59P_3

PM_IO_56

2.5V

 

 

 

 

 

D11

AG14

IO_L69P_4

PM_IO_76

2.5V

 

 

 

 

 

D12

AF14

IO_L69N_4

PM_IO_77

2.5V

 

 

 

 

 

D13

AA6

IO_L44P_3

PM_IO_26

2.5V

 

 

 

 

 

ML310 User Guide

www.xilinx.com

69

UG068 (v1.01) August 25, 2004

1-800-255-7778

 

Page 68 Page 70
Image 69
Page 68 Page 70
Contents UG068 v1.01 August 25 ML310 User GuideML310 User Guide Version Revision ML310 User Guide UG068 v1.01 August 25UG068 v1.01 August 25 Table of Contents UG068 v1.01 August 25 Additional Resources Manual ContentsTypographical ConventionsHandbook Online DocumentChapter Virtex-II Pro Summary of Virtex-II Pro FeaturesRocketIO 3.125 Gb/s Transceivers PowerPC 405 CoreVirtex-II Pro Virtex-II Fpga FabricFoundation ISE Foundation FeaturesDesign Entry Introduction to Virtex-II Pro, ISE, and EDKImplementation and Configuration SynthesisFoundation ISE Board Level Integration Embedded Development KitOverview ML310 Embedded Development PlatformML310 Board ML310 Embedded Development PlatformOverview FeaturesClock Generation Board HardwareBoard Hardware DDR MemoryDDR Signaling DDR Memory ExpansionU37 DDRA2 DDRDQS02 DDRDQ31 Serial Port Fpga Uart Signaling Standards of RS-232Introduction to Serial Ports RS-232 on the ML310Board Bring-Up System ACE CF ControllerXC2VP30 Connectivity Non-Volatile Storage6JTAG Connections to the XC2VP30 and System ACE Jtag Connection to XC2VP30System ACE Jtag Configuration Interface Gpio LEDs and LCDParallel Cable IV Interface 8LEDs and LCD Connectivity Gpio LED Interface UCF Signal Name Translator U37 J13 U35Gpio LCD Interface U37 Name U36CPU Debug and CPU Trace CPU Debug DescriptionBuffer U33 J13 9Combined Trace/Debug Connector Pinout CPU Debug Connector Pinout PCI BusCPU Debug Connection to XC2VP30 ML310 Embedded Development Platform 11 PCI Bus and Device Connectivity Pciinta Pciintb Pciintc Pcipar Pcippar Pcirstn Pciprstn 113.3V Primary PCI Bus Information Device Vendor ALi South Bridge Interface, M1535D+, U15Device Name Bus 125.0V Secondary PCI Bus Information Device Name Vendor12ALi South Bridge Interface, M1535D+, U15 Parallel Port Interface, connector assembly P1Serial Port Interface, connector assembly P1 USB, connector assembly J3 IDE, connectors J15 and J16 GPIO, connector J5 System Management Bus SMBus17Type of Gpio Available on Header J5 ALi Gpio Types Number AC97 Audio 19Audio Jacks, J1 and J2 Signal name DescriptionFlash ROM, U4 PS/2 Keyboard/Mouse Interface, connector P2Intel GD82559 Ethernet Controller Intel GD82559, U11, 10/100 Ethernet ControllerIIC/SMBus Interface IIC/SMBus SignalingIntroduction to IIC/SMBus IIC/SMBus on ML310 Board22shows the Fpga connections to all SMBus and IIC devices 14SMBus and IIC Block Diagram Serial Peripheral Interface SPI SPI SignalingPush Buttons, Switches, Front Panel Interface and Jumpers SPI AddressingPush Buttons CPU Reset, SW2 System ACE Configuration Dipswitch, SW316SW3 SysACE CFG Switch Detail Front Panel Interface Connector, J23SYACECFGA0 Jumpers Voltage JumperJ10 J11 Coupling MGT Bref Clock Selection Jumpers, J20 and J21 ATX Power Distribution and Voltage Regulation17ATX Power Distribution and Voltage Regulation 18Voltage Monitor High-Speed I/O High-Speed I/O19Personality Module Connected to ML310 Board ML310 PM ConnectorsPM2 Connector PM1 ConnectorML310 PM Utility Pins Adapter Board PM ConnectorsContact Order PM1 Power and Ground ML310 PM User I/O PinsPM2 Power and Ground PM1 User I/ORXPPAD4 RXPPAD4A25 31 PM1 Pinout RXPPAD21 RXPPAD21AK25 ML310 PM2 User I/O32 PM2 Pinout AA5
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