Xilinx Understanding AC97 Audio Features, AC97 Pinout, and LM4550 Integration

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Chapter 2: ML310 Embedded Development Platform

send byte/receive byte/ write byte/write word/read word/block read/block write command with clock synchronization function as well as 10-bit addressing ability. Please see Section “IIC/SMBus Interface” for more information regarding the devices that are connected to the SMBus. Please review the ALi M1535D+ Data sheets for more detailed information.

AC97 Audio

The ALi South Bridge has a built-in Audio that is combined with a standard AC97 CODEC, LM4550. Below is a list of the features available to the user. The ALi M1535D+ is used in conjunction with an LM4550. Please review the ALi M1535D+ and LM4550 Data sheets, located on the ML310 CDROM, for more detailed information.

♦AC97 CODEC 2.1 Specification Compliant

♦CODEC Variable Sample Rate Support

♦32-voice Hardware Wave-table Synthesis

♦32 Independent DMA _channels

♦3D Positioning Sound Acceleration

♦Legacy Sound Blaster compatible

♦FM OPL3 emulation

♦MIDI Interpretation

♦MIDI MPU-401 interface

The ML310 employs a National Semiconductor, LM4550, Audio CODEC combined with the ALi South Bridge AC97 interface. This interface can be used to play and record audio. The LM4550 has a left and right channel Line inputs, a microphone input, left and right channel line outputs and an amplified version headphone output suitable for driving an 8 ohm load via LM4880 (U2). The audio jacks are available on the J1 and J2 connector assemblies. Please consult the M1535D+, LM4550 and LM4880 data sheets in conjunction with the ML310 schematics for more details on the ML310 Audio interface.

Table 2-19describes the audio jacks available to the user on the ML310.

Table 2-19:Audio Jacks, J1 and J2

Audio Jack	Signal name	Description

J1 top	AC _AMP_OUTR	AC Amplified Output,
	AC _AMP_OUTL	driven by U2, LM4880

J1 Bottom	AC_MIC_IN	Microphone Input to U1, LM4550

J2 Top	AC _LINE_OUTR	AC Line Output, Left and Right channels,
	AC _LINE_OUTL	driven by U1, LM4550

J2 Bottom	AC _LINE_INR	AC Line Input, Left and Right channels,
	AC_LINE_INL	driven by U1, LM4550

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Contents ML310 User Guide UG068 v1.01 August 25ML310 User Guide ML310 User Guide UG068 v1.01 August 25 Version RevisionUG068 v1.01 August 25 Table of Contents UG068 v1.01 August 25 Manual Contents Additional ResourcesConventions TypographicalOnline Document HandbookChapter Summary of Virtex-II Pro Features Virtex-II ProPowerPC 405 Core RocketIO 3.125 Gb/s TransceiversVirtex-II Fpga Fabric Virtex-II ProDesign Entry Foundation FeaturesFoundation ISE Introduction to Virtex-II Pro, ISE, and EDKSynthesis Implementation and ConfigurationFoundation ISE Embedded Development Kit Board Level IntegrationML310 Embedded Development Platform OverviewML310 Embedded Development Platform ML310 BoardFeatures OverviewBoard Hardware Clock GenerationDDR Memory Board HardwareDDR Memory Expansion DDR SignalingU37 DDRA2 DDRDQS02 DDRDQ31 Introduction to Serial Ports Signaling Standards of RS-232Serial Port Fpga Uart RS-232 on the ML310System ACE CF Controller Board Bring-UpNon-Volatile Storage XC2VP30 ConnectivityJtag Connection to XC2VP30 6JTAG Connections to the XC2VP30 and System ACEGpio LEDs and LCD System ACE Jtag Configuration InterfaceParallel Cable IV Interface 8LEDs and LCD Connectivity Gpio LCD Interface UCF Signal Name Translator U37 J13 U35Gpio LED Interface U37 Name U36CPU Debug Description CPU Debug and CPU TraceBuffer U33 J13 9Combined Trace/Debug Connector Pinout PCI Bus CPU Debug Connector PinoutCPU Debug Connection to XC2VP30 ML310 Embedded Development Platform 11 PCI Bus and Device Connectivity Pciinta Pciintb Pciintc Pcipar Pcippar Pcirstn Pciprstn Device Name Bus ALi South Bridge Interface, M1535D+, U15113.3V Primary PCI Bus Information Device Vendor 125.0V Secondary PCI Bus Information Device Name VendorParallel Port Interface, connector assembly P1 12ALi South Bridge Interface, M1535D+, U15Serial Port Interface, connector assembly P1 USB, connector assembly J3 IDE, connectors J15 and J16 System Management Bus SMBus GPIO, connector J517Type of Gpio Available on Header J5 ALi Gpio Types Number 19Audio Jacks, J1 and J2 Signal name Description AC97 AudioPS/2 Keyboard/Mouse Interface, connector P2 Flash ROM, U4Intel GD82559, U11, 10/100 Ethernet Controller Intel GD82559 Ethernet ControllerIntroduction to IIC/SMBus IIC/SMBus SignalingIIC/SMBus Interface IIC/SMBus on ML310 Board22shows the Fpga connections to all SMBus and IIC devices 14SMBus and IIC Block Diagram SPI Signaling Serial Peripheral Interface SPISPI Addressing Push Buttons, Switches, Front Panel Interface and JumpersPush Buttons System ACE Configuration Dipswitch, SW3 CPU Reset, SW2Front Panel Interface Connector, J23 16SW3 SysACE CFG Switch DetailSYACECFGA0 Voltage Jumper JumpersJ10 J11 Coupling ATX Power Distribution and Voltage Regulation MGT Bref Clock Selection Jumpers, J20 and J2117ATX Power Distribution and Voltage Regulation 18Voltage Monitor High-Speed I/O High-Speed I/OML310 PM Connectors 19Personality Module Connected to ML310 BoardPM1 Connector PM2 ConnectorAdapter Board PM Connectors ML310 PM Utility PinsContact Order PM2 Power and Ground ML310 PM User I/O PinsPM1 Power and Ground PM1 User I/ORXPPAD4 RXPPAD4A25 31 PM1 Pinout ML310 PM2 User I/O RXPPAD21 RXPPAD21AK2532 PM2 Pinout AA5