Xilinx ML310 manual Embedded Development Kit, Board Level Integration

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Chapter 1: Introduction to Virtex-II Pro, ISE, and EDK

Board Level Integration

Xilinx understands the critical issues such as complex board layout, signal integrity, high- speed bus interface, high-performance I/O bandwidth, and electromagnetic interference for system level designers.

To ease the system level designers’ challenge, ISE provides support to all Xilinx leading FPGA technologies:

System IO

XCITE

Digital clock management for system timing

EMI control management for electromagnetic interference

To really help you ensure your programmable logic design works in context of your entire system, Xilinx provides complete pin configurations, packaging information, tips on signal integration, and various simulation models for your board level verification including:

IBIS models

HSPICE models

STAMP models

Embedded Development Kit

The Embedded Development Kit (EDK) is Xilinx’s solution for embedded programmable systems design and supports designs using the Virtex-II Pro. EDK hardware and software development tools, combined with the advanced features of Virtex-II Pro FPGA provide you with a new level of system design.

The system design process can be loosely divided into the following tasks:

Build the software application

Simulate the hardware description

Simulate the hardware with the software application

Simulate the hardware into the FPGA using the software application in on-chip memory

Run timing simulation

Configure the bitstream for the FPGA

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ML310 User Guide

 

1-800-255-7778

UG068 (v1.01) August 25, 2004

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Contents ML310 User Guide UG068 v1.01 August 25ML310 User Guide ML310 User Guide UG068 v1.01 August 25 Version RevisionUG068 v1.01 August 25 Table of Contents UG068 v1.01 August 25 Manual Contents Additional ResourcesConventions TypographicalOnline Document HandbookChapter Summary of Virtex-II Pro Features Virtex-II ProPowerPC 405 Core RocketIO 3.125 Gb/s TransceiversVirtex-II Fpga Fabric Virtex-II ProFoundation Features Foundation ISEDesign Entry Introduction to Virtex-II Pro, ISE, and EDKSynthesis Implementation and ConfigurationFoundation ISE Embedded Development Kit Board Level IntegrationML310 Embedded Development Platform OverviewML310 Embedded Development Platform ML310 BoardFeatures OverviewBoard Hardware Clock GenerationDDR Memory Board HardwareDDR Memory Expansion DDR SignalingU37 DDRA2 DDRDQS02 DDRDQ31 Signaling Standards of RS-232 Serial Port Fpga UartIntroduction to Serial Ports RS-232 on the ML310System ACE CF Controller Board Bring-UpNon-Volatile Storage XC2VP30 ConnectivityJtag Connection to XC2VP30 6JTAG Connections to the XC2VP30 and System ACEGpio LEDs and LCD System ACE Jtag Configuration InterfaceParallel Cable IV Interface 8LEDs and LCD Connectivity UCF Signal Name Translator U37 J13 U35 Gpio LED InterfaceGpio LCD Interface U37 Name U36CPU Debug Description CPU Debug and CPU TraceBuffer U33 J13 9Combined Trace/Debug Connector Pinout PCI Bus CPU Debug Connector PinoutCPU Debug Connection to XC2VP30 ML310 Embedded Development Platform 11 PCI Bus and Device Connectivity Pciinta Pciintb Pciintc Pcipar Pcippar Pcirstn Pciprstn ALi South Bridge Interface, M1535D+, U15 113.3V Primary PCI Bus Information Device VendorDevice Name Bus 125.0V Secondary PCI Bus Information Device Name VendorParallel Port Interface, connector assembly P1 12ALi South Bridge Interface, M1535D+, U15Serial Port Interface, connector assembly P1 USB, connector assembly J3 IDE, connectors J15 and J16 System Management Bus SMBus GPIO, connector J517Type of Gpio Available on Header J5 ALi Gpio Types Number 19Audio Jacks, J1 and J2 Signal name Description AC97 AudioPS/2 Keyboard/Mouse Interface, connector P2 Flash ROM, U4Intel GD82559, U11, 10/100 Ethernet Controller Intel GD82559 Ethernet ControllerIIC/SMBus Signaling IIC/SMBus InterfaceIntroduction to IIC/SMBus IIC/SMBus on ML310 Board22shows the Fpga connections to all SMBus and IIC devices 14SMBus and IIC Block Diagram SPI Signaling Serial Peripheral Interface SPISPI Addressing Push Buttons, Switches, Front Panel Interface and JumpersPush Buttons System ACE Configuration Dipswitch, SW3 CPU Reset, SW2Front Panel Interface Connector, J23 16SW3 SysACE CFG Switch DetailSYACECFGA0 Voltage Jumper JumpersJ10 J11 Coupling ATX Power Distribution and Voltage Regulation MGT Bref Clock Selection Jumpers, J20 and J2117ATX Power Distribution and Voltage Regulation 18Voltage Monitor High-Speed I/O High-Speed I/OML310 PM Connectors 19Personality Module Connected to ML310 BoardPM1 Connector PM2 ConnectorAdapter Board PM Connectors ML310 PM Utility PinsContact Order ML310 PM User I/O Pins PM1 Power and GroundPM2 Power and Ground PM1 User I/ORXPPAD4 RXPPAD4A25 31 PM1 Pinout ML310 PM2 User I/O RXPPAD21 RXPPAD21AK2532 PM2 Pinout AA5