Xilinx ML310 manual Parallel Port Interface, connector assembly P1

Page 41

Board Hardware

R

ALi M1535D+ supports the following features:

♦1 parallel and 2 serial ports

♦2 USB ports

♦2 IDE connectors

♦GPIO

♦SMBus Interface

♦AC97 Audio CODEC

♦PS/2 keyboard and mouse

U37

IDSEL

PCI_BUS

FPGA

	PCI_P_AD24
				U15
	PCI_P_CLK3			U15
	PCI_P_CLK3			ALi
				ALi
				South Bridge

PCI_P_AD17		IDSEL	Device ID	Vendor ID
		Audio	0x5451	0x10B9
PCI_P_AD18

		S. Bridge	0x1533	0x10B9
PCI_P_AD19

		Modem	0x5457	0x10B9
PCI_P_AD26

		USB#2	0x5237	0x10B9
PCI_P_AD27

		IDE Bus	0x5229	0x10B9
PCI_P_AD31

		USB#1	0x5237	0x10B9

PCI_BUS

X4

OSC 32.768 MHz

X2

OSC 48MHz

X3

OSC

14.3181 MHz

U1

AC97

X1

OSC

24.576 MHz


USB		USB
1		2

J3


SERIAL		Parallel		SERIAL
1		Port		2

P1

PS/2

KBD

P2

GPIO

J5

FLASH

U4

PRIMARY IDE

SECONDARY IDE

J16/J15

Figure 2-12:ALi South Bridge Interface, M1535D+, U15

Parallel Port Interface, connector assembly P1

The Parallel Port interface of the ALi South Bridge is connected to a 25 Pin connector, female DB25, which is part of the P1 connector assembly. The ALi M1535D+ supports various Parallel Port modes such as Standard Mode (SPP), Enhanced Parallel Port (EPP) and IEEE 1284 Compatible ECP. The P1, female DB25, connector pinout is configured as per IEEE Std. 1284-1994. Please review the ALi M1535D+ data sheets for more detailed information.

ML310 User Guide	www.xilinx.com	41
UG068 (v1.01) August 25, 2004	1-800-255-7778

Image 41

Contents UG068 v1.01 August 25 ML310 User GuideML310 User Guide Version Revision ML310 User Guide UG068 v1.01 August 25UG068 v1.01 August 25 Table of Contents UG068 v1.01 August 25 Additional Resources Manual ContentsTypographical ConventionsHandbook Online DocumentChapter Virtex-II Pro Summary of Virtex-II Pro FeaturesRocketIO 3.125 Gb/s Transceivers PowerPC 405 CoreVirtex-II Pro Virtex-II Fpga FabricFoundation ISE Foundation FeaturesDesign Entry Introduction to Virtex-II Pro, ISE, and EDKFoundation ISE Implementation and ConfigurationSynthesis Board Level Integration Embedded Development KitOverview ML310 Embedded Development PlatformML310 Board ML310 Embedded Development PlatformOverview FeaturesClock Generation Board HardwareBoard Hardware DDR MemoryU37 DDR SignalingDDR Memory Expansion DDRA2 DDRDQS02 DDRDQ31 Serial Port Fpga Uart Signaling Standards of RS-232Introduction to Serial Ports RS-232 on the ML310Board Bring-Up System ACE CF ControllerXC2VP30 Connectivity Non-Volatile Storage6JTAG Connections to the XC2VP30 and System ACE Jtag Connection to XC2VP30Parallel Cable IV Interface System ACE Jtag Configuration InterfaceGpio LEDs and LCD 8LEDs and LCD Connectivity Gpio LED Interface UCF Signal Name Translator U37 J13 U35Gpio LCD Interface U37 Name U36Buffer U33 J13 CPU Debug and CPU TraceCPU Debug Description 9Combined Trace/Debug Connector Pinout CPU Debug Connection to XC2VP30 CPU Debug Connector PinoutPCI Bus ML310 Embedded Development Platform 11 PCI Bus and Device Connectivity Pciinta Pciintb Pciintc Pcipar Pcippar Pcirstn Pciprstn 113.3V Primary PCI Bus Information Device Vendor ALi South Bridge Interface, M1535D+, U15Device Name Bus 125.0V Secondary PCI Bus Information Device Name Vendor12ALi South Bridge Interface, M1535D+, U15 Parallel Port Interface, connector assembly P1Serial Port Interface, connector assembly P1 USB, connector assembly J3 IDE, connectors J15 and J16 17Type of Gpio Available on Header J5 ALi Gpio Types Number GPIO, connector J5System Management Bus SMBus AC97 Audio 19Audio Jacks, J1 and J2 Signal name DescriptionFlash ROM, U4 PS/2 Keyboard/Mouse Interface, connector P2Intel GD82559 Ethernet Controller Intel GD82559, U11, 10/100 Ethernet ControllerIIC/SMBus Interface IIC/SMBus SignalingIntroduction to IIC/SMBus IIC/SMBus on ML310 Board22shows the Fpga connections to all SMBus and IIC devices 14SMBus and IIC Block Diagram Serial Peripheral Interface SPI SPI SignalingPush Buttons Push Buttons, Switches, Front Panel Interface and JumpersSPI Addressing CPU Reset, SW2 System ACE Configuration Dipswitch, SW316SW3 SysACE CFG Switch Detail Front Panel Interface Connector, J23SYACECFGA0 J10 J11 Coupling JumpersVoltage Jumper MGT Bref Clock Selection Jumpers, J20 and J21 ATX Power Distribution and Voltage Regulation17ATX Power Distribution and Voltage Regulation 18Voltage Monitor High-Speed I/O High-Speed I/O19Personality Module Connected to ML310 Board ML310 PM ConnectorsPM2 Connector PM1 ConnectorContact Order ML310 PM Utility PinsAdapter Board PM Connectors PM1 Power and Ground ML310 PM User I/O PinsPM2 Power and Ground PM1 User I/ORXPPAD4 RXPPAD4A25 31 PM1 Pinout RXPPAD21 RXPPAD21AK25 ML310 PM2 User I/O32 PM2 Pinout AA5