Additional Configuration and Maintenance Tasks
mode. Regardless of the setting of the Break enable bit in the software configuration register, pressing the Break key during approximately the first 5 seconds of booting causes a return to the ROM monitor.
Bit 9 is not used.
Bit 10 of the software configuration register controls the host portion of the IP broadcast address. Setting bit 10 causes the processor to use all zeros in the host portion of the IP broadcast address; clearing bit 10 (the factory default) causes the processor to use all ones. Bit 10 interacts with bit 14, which controls the network and subnet portions of the IP broadcast address.
Table 11 shows the combined effect of bits 10 and 14.
Table 11 |
| Configuration Register Settings for Broadcast Address | ||
|
| Destination | ||
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|
|
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|
Bit 14 | Bit 10 |
| Address (<net> <host>) | |
|
|
|
|
|
Off | Off |
| <ones> <ones> | |
|
|
|
|
|
Off | On |
| <zeros> <zeros> | |
|
|
|
|
|
On | On |
| <net> <zeros> | |
|
|
|
|
|
On | Off |
| <net> <ones> | |
|
|
|
|
|
Bits 11 and 12 of the software configuration register determine the data transmission rate of the console terminal. Table 12 shows the bit settings for the four available data transmission rates. The
Table 12 |
| System Console Terminal Data Transmission Rate Settings | ||
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|
|
|
|
Bit 12 | Bit 11 |
| Data Transmission Rate (bps) | |
|
|
|
|
|
0 | 0 |
| 9600 |
|
|
|
|
|
|
0 | 1 |
| 4800 |
|
|
|
|
|
|
1 | 0 |
| 1200 |
|
|
|
|
|
|
1 | 1 |
| 2400 |
|
|
|
|
|
|
| Performance Route Processor Installation and Configuration Guide |
60 |
