Fluke RPM4 Oper, RQS/MSS ESB MAV Error RSR, Pon Urq, Exe Dde Qye Rqc Opc, Meas Ndry RDY Nrdy

4. REMOTE OPERATION

Status Byte Register

(“∗STB?” or ”∗SRE n”)

OPER

(128)

RQS/MSS

(64)

ESB

(32)

MAV

(16)

N/A

(8)

ERROR

(4)

N/A

(2)

RSR

(1)

			Standard Event Status Register
			(“∗ESR?” or “∗ESE n”)
←←←	PON	URQ	CMD	EXE	DDE	QYE	RQC	OPC
	(128)	(64)	(32)	(16)	(8)	(4)	(2)	(1)

←←←OUTPUT

QUEUE

←←←ERROR QUEUE

			Ready Event Status Register
			(“RSR?”	or ” RSE n”)
	N/A	MEAS	NDRY	RDY	N/A	MEAS	NRDY	RDY
←←←	(128)	HI	HI	LO	(8)	HI	HI	HI
		(64)	(32)	(16)		(4)	(2)	(1)

Figure 6. Status Register Schematic

The Status Byte Register can be read using the “*STB?” query, or by performing a serial poll on the IEEE-488 bus. If you read this using a serial poll then Bit 6 is the RQS. If the “*STB?” query is used, then bit 6 is the MSS bit. All of the other bits are common to both types of query.

Each of these status bits can cause a SRQ to occur. The Service Request Enable Register (“*SRE” program message ) determines which of these flags are able to assert the SRQ line. This enable register has a matching set of bits that each will enable the designated bit to cause a SRQ, except for the RQS/MSS bit(s) which cannot cause a SRQ. If you set this register to 20 ($14 hex), an SRQ will occur if the MAV or the ERROR bit are set. The description of these bits are given as:

OPER N/A Bit 7 (128)

RQS Requested Service Bit 6 (64)

Indicates that the SRQ line of the IEEE-488 interface has been asserted by the RPM4. This bit is cleared when a serial poll is performed on the RPM4, and is a part of the Status Byte Register when read using a serial poll. This bit does not apply if the COM1 port is being used.

MSS Master Summary Status Bit 6 (64)

Indicates that an event or events occurred that caused the RPM4 to request service from the Host, much like the RQS bit. Unlike the RQS bit, it is READ ONLY and can be only cleared when the event(s) that caused the service request are cleared.

ESB Event Summary Bit 5 (32)

Indicates if an enabled bit in the Standard Event Status Register became set (see Section 4.5.3).

MAV Message Available Bit 4 (16)

Indicates that at least one reply message is waiting in the RPM4 IEEE-488 output queue.

ERROR Error Queue Not Empty Bit 2 (4)

Indicates that at least one command error message is waiting in the RPM4 IEEE- 488 error message queue. Use the “ERR?” query to get this message.

RSR Ready Summary Bit 0 (1)

Indicates that an enabled bit in the Ready Status Register became set.

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