Main
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FIGURES
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TABL ES
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CHAPTER 1 GUIDE TO THIS MANUAL
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CHAPTER 2 ARCHITECTURAL OVERVIEW
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2-3
ARCHITECTURAL OVERVIEW
Figure 2-2. Clock Circuitry (87C196LA, LB Only)
F
F
2F
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ARCHITECTURAL OVERVIEW
Figure 2-4. Effect of Clock Mode on Internal CLKOUT Frequency
Table 2-3. Relationships Between Input Frequency, Clock Multiplier, and State Times
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CHAPTER 3 ADDRESS SPACE
Table 3-1. Address Map
SUPPLEMENT
NOTE
Table 3-1. Address Map (Continued)
Figure 3-1. Register File Address Map Table 3-2. Register File Memory Addresses
Upper Register File Lower Register File
Stack Pointer
Address
General-purpose Register RAM
SUPPLEMENT
Table 3-3. 8XC196L
Peripheral SFRs
Table 3-3. 8XC196L
Peripheral SFRs (Continued)
SUPPLEMENT
Table 3-4. Windows
Table 3-4. Windows (Continued)
SUPPLEMENT
Table 3-4. Windows (Continued)
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SUPPLEMENT
Table 4-1. Interrupt Sources, Vectors, and Priorities
Figure 4-1. Interrupt Mask (INT_MASK) Register
SUPPLEMENT
Figure 4-2. Interrupt Mask 1 (INT_MASK1) Register
Figure 4-3. Interrupt Pending (INT_PEND) Register
SUPPLEMENT
Figure 4-4. Interrupt Pending 1 (INT_PEND1) Register
Figure 4-5. PTS Select (PTSSEL) Register
SUPPLEMENT
Figure 4-6. PTS Service (PTSSRV) Register
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CHAPTER 5 I/O PORTS
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5-3
I/O PORTS
Figure 5-1. Ports 1, 2, 5, and 6 Internal Structure (87C196LA, LB Only)
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SUPPLEMENT
Figure 5-2. Ports 3 and 4 Internal Structure (87C196LA, LB Only)
5-6
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CHAPTER 6 SYNCHRONOUS SERIAL I/O PORT
Figure 6-1. SSIO 0 Clock (SSIO0_CLK) Register
SUPPLEMENT
Figure 6-2. SSIO 1 Clock (SSIO1_CLK) Register
SYNCHRONOUS SERIAL I/O PORT
Figure 6-2. SSIO 1 Clock (SSIO1_CLK) Register (Continued)
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CHAPTER 7 EVENT PROCESSOR ARRAY
SUPPLEMENT
Figure 7-1. EPA Block Diagram (87C196LA, LB Only)
7-2
7-3
EVENT PROCESSOR ARRAY
Figure 7-2. EPA Block Diagram (83C196LD Only)
SUPPLEMENT
Figure 7-4. EPA Interrupt Mask 1 (EPA_MASK1) Register
Figure 7-3. EPA Interrupt Mask (EPA_MASK) Register
EVENT PROCESSOR ARRAY
Figure 7-6. EPA Interrupt Pending 1 (EPA_PEND1) Register
Figure 7-5. EPA Interrupt Pending (EPA_PEND) Register
SUPPLEMENT
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CHAPTER 8 J1850 COMMUNICATIONS CONTROLLER
SUPPLEMENT
8-2
Figure 8-2. J1850 Communications Controller Block Diagram
Peripheral Data Bus
Table 8-1. J1850 Controller Signals
Table 8-2. Control and Status Registers
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Figure 8-8. Definition for Start and End of Frame Symbols
Table 8-4 details the symbol timing characteristics supported by the 87C196LB.
Table 8-4. Huntzicker Symbol Timing Characteristics
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Figure 8-10. IFR Type 2 Message Frame 8.4.2.3 IFR Messaging Type 3: Multiple Bytes, Single Responder
. . . . . . . . . .
Figure 8-11. IFR Type 3 Message Frame
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Figure 8-16. J1850 Command (J_CMD) Register
SUPPLEMENT
Figure 8-17. J1850 Configuration (J_CFG) Register
J1850 COMMUNICATIONS CONTROLLER
Figure 8-17. J1850 Configuration (J_CFG) Register (Continued)
SUPPLEMENT
Figure 8-18. J1850 Delay (J_DLY) Register
Figure 8-19. J1850 Status (J_STAT) Register
SUPPLEMENT
Figure 8-19. J1850 Status (J_STAT) Register (Continued)
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CHAPTER 9 MINIMUM HARDWARE CONSIDERATIONS
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8XC196L
SUPPLEMENT
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10-2
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CHAPTER 11 PROGRAMMING THE NONVOLATILE MEMORY
SUPPLEMENT
Table 11-2. 87C196LA, LB
OTPROM Address Map
11-3
PROGRAMMING THE NONVOLATILE MEMORY
10
EA#
dynamic failure analysis of the device is impossible.
Figure 11-1. Slave Programming Circuit Table 11-3. Slave Programming Mode Address Map
SUPPLEMENT
Figure 11-2. Serial Port Programming Circuit
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SUPPLEMENT
Table A-1. 87C196LA Signals Arranged by Functional Categories
Figure A-1. 87C196LA 52-pin PLCC Package
A3419-03
A-3
xx87C196LA20 View of component as mounted on PC board
SUPPLEMENT
Table A-2. 87C196LB Signals Arranged by Functional Categories
Figure A-2. 87C196LB 52-pin PLCC Package
A3361-03
A-5
xx87C196LB20 View of component as mounted on PC board
SUPPLEMENT
Table A-3. 83C196LD Signals Arranged by Functional Categories
A-7
Figure A-3. 83C196LD 52-pin PLCC Package
Table A-4. Definition of Status Symbols
xx83C196LD View of component as mounted on PC board
SUPPLEMENT
Table A-5. 87C196LA, LB Default Signal Conditions
Table A-6. 83C196LD Default Signal Conditions
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GLOSSARY
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INDEX
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D
P
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