Intel 87C196CA, 8XC196Jx, 8XC196Lx, 8XC196Kx user manual EPA Pending Registers, Epapend, EPAPEND1

EVENT PROCESSOR ARRAY

7.1.2EPA Pending Registers

Figures 7-5 and 7-6 illustrate the EPA pending registers, EPA_PEND and EPA_PEND1, for the 8XC196Lx microcontroller family.

EPA_PEND	Address:	1FA2H
	Reset State:	0000H

When hardware detects a pending EPA6–9 or OVR0–3, 8–9 interrupt request, it sets the corresponding bit in the EPA interrupt pending register (EPA_PEND or EPA_PEND1). The EPAIPV register contains a number that identifies the highest priority, active, shared interrupt source. When EPAIPV is read, the EPA interrupt pending bit associated with the EPAIPV priority value is cleared.

	15									8
Lx		—	—	EPA6	EPA7	EPA8	EPA9		OVR0	OVR1
		7								0
		0VR2	OVR3	—	—	—	—		OVR8	OVR9
Bit					Function
Number
15:0†	Any set bit indicates that the corresponding EPAx interrupt source is pending. The bit is
	cleared when software reads the EPA interrupt priority vector register (EPAIPV).
† Bits 2–5 and 14–15 are reserved on the 8XC196Lx device family. For compatibility with future
devices, write zeros to these bits.
		Figure 7-5. EPA Interrupt Pending (EPA_PEND) Register
EPA_PEND1								Address:		1FA6H
							Reset State:			00H

When hardware detects a pending EPAx interrupt, it sets the corresponding bit in the EPA interrupt pending register (EPA_PEND or EPA_PEND1). The EPAIPV register contains a number that identifies the highest priority, active, multiplexed interrupt source. When EPAIPV is read, the EPA interrupt pending bit associated with the EPAIPV priority value is cleared.

7				0
—	—	—	—		COMP0†	COMP1†	OVRTM1	OVRTM2
Bit					Function
Number
7:4	Reserved; always write as zeros.
3:0†	Any set bit indicates that the corresponding EPAx interrupt source is pending. The bit is
	cleared when the EPA interrupt priority vector register (EPAIPV) is read.
	† 87C196LA, LB only; reserved on 83C196LD.

Figure 7-6. EPA Interrupt Pending 1 (EPA_PEND1) Register

7-5