Intel 8XC196Jx, 8XC196Lx, 8XC196Kx, 87C196CA instruction

8XC196LX SUPPLEMENT

(J_CFG.7) and considers whether the IFR message response has a CRC byte appended. Figure 8-7 depicts the SAE preferred, active-level state bit format timing for the NB.

1			64µS	1			128µS

				or
0				0
						NB for IFR with CRC
NB for IFR without CRC

A5220-01

Figure 8-7. Huntzicker Symbol Definition for the Normalization Bit

8.4.1.4Start and End Message Frame Symbols

Five symbols are used to mark the start and end of a message frame and to allow the J1850 bus to properly recognize the interruption of a message transmission or reception. Figure 8-8 illus- trates the formats and their respective timing.

The following is a description of each symbol:

•start of frame (SOF) — this symbol signals the start of a message frame. This is an active- level state symbol only and appears once per frame.

•end of data (EOD) — this symbol signals the end of the data transmission. This is a passive- level state symbol only. It appears twice in IFR messaging: at the end of the initial request data field and at the end of the IFR data field.

•end of frame (EOF) — this symbol signals the end of a message frame and returns the bus to an idle state. This is a passive-level state symbol only. It appears once per frame.

•in-frame separation (IFS) — the timing of this symbol allows for proper synchronization of multiple nodes during back-to-back transmissions. Nodes contending for the bus must comply with one of two conditions before transmitting:

—wait for the IFS minimum timing to expire

—wait for a rising edge on the bus after the EOF minimum timing has expired

•break (BRK) — this symbol signals an interruption during a bus transmission. At the point of termination, all nodes are reset. This is an active-level state symbol.

8-10

Image 76

Intel 8XC196Jx, 8XC196Lx, 8XC196Kx, 87C196CA user manual 64µS 128µS NB for IFR with CRC NB for IFR without CRC

Contents

August Page Contents 8XC196LX Supplement Chapter Synchronous Serial I/O Port Entering and Exiting Once Mode Functional Groupings of Signals Default ConditionsProgramming the J1850 Controller Internal Timing Figures 11-3 Tables Guide to This Manual Page Manual Contents Chapter Guide to this Manual Related Documents Related Documents Architectural Overview Page Features of the 8XC196Lx and 8XC196Kx Product Famiies Microcontroller FeaturesChapter Architectural Overview Block Diagram Internal Timing Clock Circuitry 87C196LA, LB Only State Times at Various Frequencies MHz12 MHz 16 MHz Pllen External TimingMultiplier State Time Uprom Programming Values and Locations Internal PeripheralsCLK1 CLK0 1 I/O Ports Synchronous Serial I/O PortEvent Processor Array 4 J1850 Communications ControllerPage Address Space Page Address Partitions Chapter Address SpaceAddress Map Register File 1BFF CA,JT,KT AddressJR, KR XC196Lx Peripheral SFRs Peripheral SPECIAL-FUNCTION RegistersUSFR1 LA, LB SSIO1CLK SSIO0CLKRstsrc Jdly Windowing Windows Upper Register File CA, JT, JV, KT BaseUpper Register File CA, JT, JV, KT, LA, LB 0140H 4BH25H 0120H 49H 0100H 48H 24H 12H Standard and PTS Interrupts Page Chapter Standard and PTS Interrupts Interrupt SOURCES, VECTORS, and Priorities Interrupt Controller PTS Service Interrupt RegistersInterrupt Sources, Vectors, and Priorities Interrupt Source Mnemonic Priority Name Interrupt Mask Registers IntmaskBit Function Number Bit Mnemonic Interrupt Description Interrupt Pending Registers INTMASK1LA, LD NMI Extint SSIO1 SSIO0 Interrupt Pending Intpend Register Intpend INTPEND1 Peripheral Transaction Server RegistersNMI Bit PtsselInterrupt PTS Vector Bits PtssrvInterrupt Standard Vector Ports Page Chapter Ports I/O Ports OverviewMicrocontroller Ports EPA, Ssio 8XC196LX Supplement Configuring Ports 1, 2, 5, and 6 Bidirectional Ports Ports 1, 2, 5, and 6 Internal Structure 87C196LA, LB Only For complementary output configurations Special Bidirectional Port Considerations Internal Structure for Ports 3 and 4 ADDRESS/DATA BUS 8XC196L X Supplement Synchronous Serial Port Page Chapter Synchronous Serial I/O Port Ssio 0 Clock RegisterBit Function For receptions Ssio 1 Clock Register 1FB7HCHS DUP Conint Conpnd Phas Pols CHS SSIO1CLK Page Event Processor Array Page Chapter Event Processor Array EPA Functional OverviewEPA Channels Device Capture/Compare Compare-only EPA Block Diagram 87C196LA, LB Only EPA Block Diagram 83C196LD Only Epamask EPA Mask RegistersEPAMASK1 Epapend EPA Pending RegistersEPAPEND1 Value Interrupt EPA Interrupt Priority Vector RegisterEpaipv J1850 Communications Controller Page J1850 Functional Overview J1850 Communications ControllerPLL Clkout J1850 Communications Controller Block Diagram J1850 Controller Signals and Registers J1850 Controller SignalsSignal Control and Status Registers Control State Machine J1850 Controller OperationCyclic Redundancy Check Generator Symbol Synchronization and Timing Circuitry Bus ContentionError Detection Bit Arbitration Delay Compensation Symbol Encoding and DecodingClock Prescaler Digital Filter Huntzicker Symbol Definition for J1850 Bit Arbitration Example Message Frames Bit Arbitration Example Standard Messaging HeaderCRC Byte Normalization Bit 64µS 128µS NB for IFR with CRC NB for IFR without CRC Huntzicker Symbol Timing Characteristics Name Symbol Bus Level TXmin TXnom TXmax RXmin RXmax Units In-frame Response Messaging IFR Messaging Type 1 Single Byte, Single Responder Transmitting and Receiving Messages Transmitting Messages Transmit Byte CPU JTX Jtxbuf Receive Byte Receiving MessagesCPU Jrxbuf IFR Messages Programming the J1850 Command Jcmd RegisterProgramming the J1850 Controller Jcmd Auto IFR Ignore Abort MSG3 MSG2 MSG1 MSG0Auto MSG30 Operation Purpose Programming the J1850 Configuration Jcfg Register NBF IFR3 4XM Txbrk Rxpol PRE1 PRE0NBF IFR without CRC Byte Programming the J1850 Delay Compensation Jdly Register PRE1 PRE0 18. J1850 Delay Jdly Register Programming the J1850 Status Jstat Register Jstat Msgtx Msgrx Minimum Hardware Considerations Page Identifying the Reset Source Minimum Hardware Considerations Design Considerations for 8XC196LA, LB, and LD Special Operating Modes Page Chapter Special Operating Modes Entering and Exiting Once Mode 10-3 Page Programming Nonvolatile Memory Page Programming the Nonvolatile Memory Signature Word and Programming Voltage ValuesOtprom Address MAP Signature Word and Programming Voltage Values Slave Programming Circuit and Address MAP C196LA, LB Otprom Address MapAddress Range Description Hex CCB1 Description Address Comments Serial Port Programming Circuit and Address MAP Serial Port Programming Circuit Serial Port Programming Mode Address Map Description Address RangeA000-FFFFH Do not addressPage Signal Descriptions Page Appendix a Signal Descriptions Functional Groupings of Signals Table A-1 C196LA Signals Arranged by Functional Categories Signal Descriptions Table A-2 C196LB Signals Arranged by Functional Categories Figure A-2 C196LB 52-pin Plcc Package Table A-3 C196LD Signals Arranged by Functional Categories Input Name PinInput/Output Cont’d Name Pin Bus Control & Status Default Conditions Port Alternate During RESET# Upon RESET# Power Table A-5 C196LA, LB Default Signal ConditionsSignals Functions Table A-6 C196LD Default Signal Conditions Page Glossary Page ALU GlossaryBIT Byte EPA DOUBLE-WORDESD FET Integer ISR LONG-INTEGERLSB LSW MSB MSW PIC PIH PLL PTS PSWPtscb QUAD-WORD Ralu SFR SARSHORT-INTEGER Uart WDT VPWWord Index Page Index Clkout Index-2