Intel 8XC196Jx, 8XC196Lx Entering and Exiting Once Mode, Clock Circuitry 87C196LA, LB Only

8XC196LX SUPPLEMENT

XTAL1

XTAL2

Disable

PLL

(Powerdown)

FXTAL1

	XTAL1	XTAL1			PLLEN
	F	2F	1
Disable Oscillator
(Powerdown)			0
					f
				Divide by two
					Circuit

Phase	Filter
Comparator

Phase-locked

Oscillator

Phase-locked Loop

Clock Multiplier

Disable Clock Input (Powerdown)

f/2

Clock

Generators

f/2

Programmable

Divider

(CLK1:0)

Clock

Failure

Detection

To reset logic

Disable Clocks (Idle, Powerdown) CPU Clocks (PH1, PH2)

Peripheral Clocks (PH1, PH2)

OSC

0

CLKOUT

1

Disable Clocks (Powerdown)

A5290-01

Figure 10-1. Clock Circuitry (87C196LA, LB Only)

10.2 ENTERING AND EXITING ONCE MODE

ONCE mode isolates the device from other components in the system to allow printed-circuit- board testing or debugging with a clip-on emulator. During ONCE mode, all pins except XTAL1, XTAL2, VSS, and VCC are weakly pulled either high or low. During ONCE mode, RESET# must be held high or the device will exit ONCE mode and enter the reset state.

On the 87C196LA and LB, the reset state level of all 41 general-purpose I/O pins has changed from a weak logic “1” (wk1) to a weak logic “0” (wk0). ONCE shares a package with port pin

2.6.Asserting and holding the ONCE signal high during the rising edge of RESET# causes the device to enter ONCE mode. To prevent accidental entry into ONCE mode, configure this pin as

10-2