Base, Upper Register File CA, JT, JV, KT | Intel 87C196CA, 8XC196Jx

				ADDRESS SPACE
	Table 3-4. Windows (Continued)

	WSR Value		WSR Value	WSR Value for
Base	WSR Value		WSR Value	128-byte
Base	for 32-byte Window		for 64-byte Window	128-byte
Address	for 32-byte Window		for 64-byte Window	Window
Address	(00E0–00FFH)		(00C0–00FFH)	Window
	(00E0–00FFH)		(00C0–00FFH)	(0080–00FFH)
				(0080–00FFH)

Register RAM (87C196JV Only; Continued)

1CE0H	67H
1CC0H	66H		33H
1CA0H	65H
1C80H	64H		32H	19H
1C60H	63H
1C40H	62H		31H
1C20H	61H
1C00H	60H		30H	18H
Upper Register File (CA, JT, JV, KT)

03E0H	5FH
03C0H	5EH		2FH
03A0H	5DH
0380H	5CH		2EH	17H
0360H	5BH
0340H	5AH		2DH
0320H	59H
0300H	58H		2CH	16H
Upper Register File (CA, JT, JV, KT, LA, LB)

02E0H	57H
02C0H	56H		2BH
02A0H	55H
0280H	54H		2AH	15H
0260H	53H
0240H	52H		29H
0220H	51H
0200H	50H		28H	14H
Upper Register File (CA, JR, JT, JV, KR, KT, LA, LB)

01E0H	4FH
01C0H	4EH		27H
01A0H	4DH
0180H	4CH		26H	13H

NOTE: Locations 1FE0–1FFFH contain memory-mapped SFRs that cannot be accessed through a window. Reading these locations through a window returns FFH; writing these locations through a window has no effect.

3-7

Image 31

Intel 87C196CA, 8XC196Jx, 8XC196Lx, 8XC196Kx user manual Base, Upper Register File CA, JT, JV, KT, LA, LB

Contents

August Page Contents 8XC196LX Supplement Chapter Synchronous Serial I/O Port Internal Timing Entering and Exiting Once ModeFunctional Groupings of Signals Default Conditions Programming the J1850 Controller Figures 11-3 Tables Guide to This Manual Page Chapter Guide to this Manual Manual Contents Related Documents Related Documents Architectural Overview Page Features of the 8XC196Lx and 8XC196Kx Product Famiies Microcontroller FeaturesChapter Architectural Overview Internal Timing Block Diagram Clock Circuitry 87C196LA, LB Only 16 MHz State Times at Various FrequenciesMHz 12 MHz Pllen External TimingMultiplier State Time Uprom Programming Values and Locations Internal PeripheralsCLK1 CLK0 4 J1850 Communications Controller 1 I/O PortsSynchronous Serial I/O Port Event Processor ArrayPage Address Space Page Address Partitions Chapter Address SpaceAddress Map 1BFF Register File CA,JT,KT AddressJR, KR XC196Lx Peripheral SFRs Peripheral SPECIAL-FUNCTION RegistersUSFR1 LA, LB Jdly SSIO1CLKSSIO0CLK Rstsrc Windows Windowing Upper Register File CA, JT, JV, KT BaseUpper Register File CA, JT, JV, KT, LA, LB 0140H 4BH25H 0120H 49H 0100H 48H 24H 12H Standard and PTS Interrupts Page Interrupt SOURCES, VECTORS, and Priorities Chapter Standard and PTS Interrupts Interrupt Source Mnemonic Priority Name Interrupt Controller PTS ServiceInterrupt Registers Interrupt Sources, Vectors, and Priorities Bit Mnemonic Interrupt Description Interrupt Mask RegistersIntmask Bit Function Number NMI Extint SSIO1 SSIO0 Interrupt Pending RegistersINTMASK1 LA, LD Intpend Interrupt Pending Intpend Register INTPEND1 Peripheral Transaction Server RegistersNMI Bit PtsselInterrupt PTS Vector Bits PtssrvInterrupt Standard Vector Ports Page EPA, Ssio Chapter PortsI/O Ports Overview Microcontroller Ports 8XC196LX Supplement Ports 1, 2, 5, and 6 Internal Structure 87C196LA, LB Only Configuring Ports 1, 2, 5, and 6 Bidirectional Ports Special Bidirectional Port Considerations For complementary output configurations Internal Structure for Ports 3 and 4 ADDRESS/DATA BUS 8XC196L X Supplement Synchronous Serial Port Page For receptions Chapter Synchronous Serial I/O PortSsio 0 Clock Register Bit Function CHS Ssio 1 Clock Register1FB7H CHS DUP Conint Conpnd Phas Pols SSIO1CLK Page Event Processor Array Page Device Capture/Compare Compare-only Chapter Event Processor ArrayEPA Functional Overview EPA Channels EPA Block Diagram 87C196LA, LB Only EPA Block Diagram 83C196LD Only Epamask EPA Mask RegistersEPAMASK1 Epapend EPA Pending RegistersEPAPEND1 Value Interrupt EPA Interrupt Priority Vector RegisterEpaipv J1850 Communications Controller Page J1850 Functional Overview J1850 Communications ControllerPLL Clkout J1850 Communications Controller Block Diagram Control and Status Registers J1850 Controller Signals and RegistersJ1850 Controller Signals Signal Control State Machine J1850 Controller OperationCyclic Redundancy Check Generator Bit Arbitration Symbol Synchronization and Timing CircuitryBus Contention Error Detection Digital Filter Delay CompensationSymbol Encoding and Decoding Clock Prescaler Bit Arbitration Example Huntzicker Symbol Definition for J1850 Bit Arbitration Example Message Frames Normalization Bit Standard MessagingHeader CRC Byte 64µS 128µS NB for IFR with CRC NB for IFR without CRC Name Symbol Bus Level TXmin TXnom TXmax RXmin RXmax Units Huntzicker Symbol Timing Characteristics IFR Messaging Type 1 Single Byte, Single Responder In-frame Response Messaging Transmitting Messages Transmitting and Receiving Messages CPU JTX Jtxbuf Transmit Byte Receive Byte Receiving MessagesCPU Jrxbuf IFR Messages Programming the J1850 Command Jcmd RegisterProgramming the J1850 Controller MSG30 Operation Purpose JcmdAuto IFR Ignore Abort MSG3 MSG2 MSG1 MSG0 Auto IFR without CRC Byte Programming the J1850 Configuration Jcfg RegisterNBF IFR3 4XM Txbrk Rxpol PRE1 PRE0 NBF PRE1 PRE0 Programming the J1850 Delay Compensation Jdly Register 18. J1850 Delay Jdly Register Jstat Programming the J1850 Status Jstat Register Msgrx Msgtx Minimum Hardware Considerations Page Minimum Hardware Considerations Identifying the Reset Source Design Considerations for 8XC196LA, LB, and LD Special Operating Modes Page Chapter Special Operating Modes Entering and Exiting Once Mode 10-3 Page Programming Nonvolatile Memory Page Signature Word and Programming Voltage Values Programming the Nonvolatile MemorySignature Word and Programming Voltage Values Otprom Address MAP CCB1 Slave Programming Circuit and Address MAPC196LA, LB Otprom Address Map Address Range Description Hex Description Address Comments Serial Port Programming Circuit Serial Port Programming Circuit and Address MAP Do not address Serial Port Programming Mode Address MapDescription Address Range A000-FFFFHPage Signal Descriptions Page Functional Groupings of Signals Appendix a Signal Descriptions Table A-1 C196LA Signals Arranged by Functional Categories Signal Descriptions Table A-2 C196LB Signals Arranged by Functional Categories Figure A-2 C196LB 52-pin Plcc Package Bus Control & Status Table A-3 C196LD Signals Arranged by Functional CategoriesInput Name Pin Input/Output Cont’d Name Pin Default Conditions Port Alternate During RESET# Upon RESET# Power Table A-5 C196LA, LB Default Signal ConditionsSignals Functions Table A-6 C196LD Default Signal Conditions Page Glossary Page ALU GlossaryBIT Byte EPA DOUBLE-WORDESD Integer FET LSW ISRLONG-INTEGER LSB MSW MSB PIC PIH PLL PTS PSWPtscb Ralu QUAD-WORD SFR SARSHORT-INTEGER Uart WDT VPWWord Index Page Clkout Index Index-2