6-3
SYNCHRONOUS SERIAL I/O PORT
For transmissions, SSIO1_CLK determines whether the SSIO shifts out data bits on rising or fall-ing clock edges. For receptions, SSIO1_CLK determines whether the SSIO samples data bits onthe rising or falling clock edges.2 CONPND Master Contention Interrupt Pending
For channel-select master operations, the SSIO sets this bit when the
CHS# pin is externally activated. In a system with multiple masters, an
external master activates the CHS# signal to request control of the serial
clock.
This bit is valid for channel-select master operations and ignored for all
other operations.
1 PHAS Phase and Polarity Select
For normal transfers, these bits determine the idle state of the serial
clock and select the serial clock signal edge that the SSIO samples
incoming data bits or shifts out outgoing data bits.
For transmissions
PHAS POLS
0 0 low idle state; shift on falling edges
0 1 high idle state; shift on rising edges
1 0 low idle state; shift on rising edges
1 1 high idle state; shift on falling edges
For receptions
PHAS POLS
0 0 low idle state; sample on rising edges
0 1 high idle state; sample on falling edges
1 0 low idle state; sample on falling edges
1 1 high idle state; sample on rising edges
These bits are ignored for duplex and channel-select modes; these
modes use SC0 as the common clock signal. The SSIO0_CLK register
contains the phase and polarity select bits for the SC0 clock signal.
These bits are also ignored for handshaking transfers. Use SSIO1_ CON
to select the type of data transfer (normal or handshaking) for channel 1.
0POLS
SSIO1_CLK (Continued) Address:
Reset State: 1FB7H
00H
The SSIO 1 clock (SSIO1_CLK) register selects the SSIO mode of operation (standard, duplex, or
channel-select), enables the channel-select master contention interrupt request, and selects the
phase and polarity for the serial clock (SC1) for channel 1.
7 0
— — CHS DUP CONINT CONPND PHAS POLS
Bit
Number Bit
Mnemonic Function