Programming the J1850 Configuration Jcfg Register | Intel 8XC196Jx

8XC196LX SUPPLEMENT

8.6.2Programming the J1850 Configuration (J_CFG) Register

The J1850 configuration register (Figure 8-17) selects the proper oscillator prescaler, initiates a transmission break for debugging, invokes clock quadrupling operation, and selects the normal- ization bit format.

J_CFG	Address:	1F54H
	Reset State:	00H

The J1850 configuration (J_CFG) register selects the proper oscilator prescaler, initiates transmission break for debug, invokes clock quadrupling operation, and selects the normalizartion bit format. This byte register can be directly addressed through windowing. All J1850 bus activity is ignored until you first write to this register.

7

NBF	IFR3	4XM	TXBRK

0

RXPOL	—	PRE1	PRE0

Bit	Bit					Function
Number	Mnemonic					Function
Number	Mnemonic

7	NBF	Normalization Bit Format
		This bit specifies which normalization bit (NB) format is to be used.
				IFR with CRC Byte		IFR without CRC Byte
		0	=	active long NB	0 =	active short NB
		1	=	active short NB	1 =	active long NB

6	IFR3	Type 3 IFR Messaging
		This bit selects type 3 IFR messaging, which supports the in-frame transfer
		of an unspecified number of data bytes.
		0	= normal operation
		1	= type 3 IFR messaging

5	4XM	Oscillator Quadruple (4x) Mode
		This bit allows the J1850 peripheral to operate at four times the normal bit
		transfer rate (41.6 Kb/s versus 10.4 Kb/s).
		0	= normal operation
		1	= 4x mode operation

4	TXBRK	Transmission Break
		This bit will terminate any transmission in progress by writing a break (BRK)
		symbol to the bus.
		0	= normal operation
		1	= transmit BRK symbol onto bus

3	RXPOL	Receive Polarity
		This bit changes the polarity of the receive symbol.
		0	= normal operation – Rx input inverted
		1	= receive polarity enabled – Rx input non-inverted

Figure 8-17. J1850 Configuration (J_CFG) Register

8-18

Image 84

Intel 8XC196Jx, 8XC196Lx Programming the J1850 Configuration Jcfg Register, NBF IFR3 4XM Txbrk Rxpol PRE1 PRE0, Nbf

Contents

August Page Contents 8XC196LX Supplement Chapter Synchronous Serial I/O Port Entering and Exiting Once Mode Functional Groupings of Signals Default ConditionsProgramming the J1850 Controller Internal Timing Figures 11-3 Tables Guide to This Manual Page Manual Contents Chapter Guide to this Manual Related Documents Related Documents Architectural Overview Page Microcontroller Features Features of the 8XC196Lx and 8XC196Kx Product FamiiesChapter Architectural Overview Block Diagram Internal Timing Clock Circuitry 87C196LA, LB Only State Times at Various Frequencies MHz12 MHz 16 MHz External Timing PllenMultiplier State Time Internal Peripherals Uprom Programming Values and LocationsCLK1 CLK0 1 I/O Ports Synchronous Serial I/O PortEvent Processor Array 4 J1850 Communications ControllerPage Address Space Page Chapter Address Space Address PartitionsAddress Map Register File 1BFF Address CA,JT,KTJR, KR Peripheral SPECIAL-FUNCTION Registers XC196Lx Peripheral SFRsUSFR1 LA, LB SSIO1CLK SSIO0CLKRstsrc Jdly Windowing Windows Base Upper Register File CA, JT, JV, KTUpper Register File CA, JT, JV, KT, LA, LB 4BH 0140H25H 0120H 49H 0100H 48H 24H 12H Standard and PTS Interrupts Page Chapter Standard and PTS Interrupts Interrupt SOURCES, VECTORS, and Priorities Interrupt Controller PTS Service Interrupt RegistersInterrupt Sources, Vectors, and Priorities Interrupt Source Mnemonic Priority Name Interrupt Mask Registers IntmaskBit Function Number Bit Mnemonic Interrupt Description Interrupt Pending Registers INTMASK1LA, LD NMI Extint SSIO1 SSIO0 Interrupt Pending Intpend Register Intpend Peripheral Transaction Server Registers INTPEND1NMI Ptssel BitInterrupt PTS Vector Ptssrv BitsInterrupt Standard Vector Ports Page Chapter Ports I/O Ports OverviewMicrocontroller Ports EPA, Ssio 8XC196LX Supplement Configuring Ports 1, 2, 5, and 6 Bidirectional Ports Ports 1, 2, 5, and 6 Internal Structure 87C196LA, LB Only For complementary output configurations Special Bidirectional Port Considerations Internal Structure for Ports 3 and 4 ADDRESS/DATA BUS 8XC196L X Supplement Synchronous Serial Port Page Chapter Synchronous Serial I/O Port Ssio 0 Clock RegisterBit Function For receptions Ssio 1 Clock Register 1FB7HCHS DUP Conint Conpnd Phas Pols CHS SSIO1CLK Page Event Processor Array Page Chapter Event Processor Array EPA Functional OverviewEPA Channels Device Capture/Compare Compare-only EPA Block Diagram 87C196LA, LB Only EPA Block Diagram 83C196LD Only EPA Mask Registers EpamaskEPAMASK1 EPA Pending Registers EpapendEPAPEND1 EPA Interrupt Priority Vector Register Value InterruptEpaipv J1850 Communications Controller Page J1850 Communications Controller J1850 Functional OverviewPLL Clkout J1850 Communications Controller Block Diagram J1850 Controller Signals and Registers J1850 Controller SignalsSignal Control and Status Registers J1850 Controller Operation Control State MachineCyclic Redundancy Check Generator Symbol Synchronization and Timing Circuitry Bus ContentionError Detection Bit Arbitration Delay Compensation Symbol Encoding and DecodingClock Prescaler Digital Filter Huntzicker Symbol Definition for J1850 Bit Arbitration Example Message Frames Bit Arbitration Example Standard Messaging HeaderCRC Byte Normalization Bit 64µS 128µS NB for IFR with CRC NB for IFR without CRC Huntzicker Symbol Timing Characteristics Name Symbol Bus Level TXmin TXnom TXmax RXmin RXmax Units In-frame Response Messaging IFR Messaging Type 1 Single Byte, Single Responder Transmitting and Receiving Messages Transmitting Messages Transmit Byte CPU JTX Jtxbuf Receiving Messages Receive ByteCPU Jrxbuf Programming the J1850 Command Jcmd Register IFR MessagesProgramming the J1850 Controller Jcmd Auto IFR Ignore Abort MSG3 MSG2 MSG1 MSG0Auto MSG30 Operation Purpose Programming the J1850 Configuration Jcfg Register NBF IFR3 4XM Txbrk Rxpol PRE1 PRE0NBF IFR without CRC Byte Programming the J1850 Delay Compensation Jdly Register PRE1 PRE0 18. J1850 Delay Jdly Register Programming the J1850 Status Jstat Register Jstat Msgtx Msgrx Minimum Hardware Considerations Page Identifying the Reset Source Minimum Hardware Considerations Design Considerations for 8XC196LA, LB, and LD Special Operating Modes Page Chapter Special Operating Modes Entering and Exiting Once Mode 10-3 Page Programming Nonvolatile Memory Page Programming the Nonvolatile Memory Signature Word and Programming Voltage ValuesOtprom Address MAP Signature Word and Programming Voltage Values Slave Programming Circuit and Address MAP C196LA, LB Otprom Address MapAddress Range Description Hex CCB1 Description Address Comments Serial Port Programming Circuit and Address MAP Serial Port Programming Circuit Serial Port Programming Mode Address Map Description Address RangeA000-FFFFH Do not addressPage Signal Descriptions Page Appendix a Signal Descriptions Functional Groupings of Signals Table A-1 C196LA Signals Arranged by Functional Categories Signal Descriptions Table A-2 C196LB Signals Arranged by Functional Categories Figure A-2 C196LB 52-pin Plcc Package Table A-3 C196LD Signals Arranged by Functional Categories Input Name PinInput/Output Cont’d Name Pin Bus Control & Status Default Conditions Table A-5 C196LA, LB Default Signal Conditions Port Alternate During RESET# Upon RESET# PowerSignals Functions Table A-6 C196LD Default Signal Conditions Page Glossary Page Glossary ALUBIT Byte DOUBLE-WORD EPAESD FET Integer ISR LONG-INTEGERLSB LSW MSB MSW PIC PIH PLL PSW PTSPtscb QUAD-WORD Ralu SAR SFRSHORT-INTEGER Uart VPW WDTWord Index Page Index Clkout Index-2