8XC196L
X

SUPPLEMENT

8-18
8.6.2 Programming the J1850 Configuration (J_CFG) RegisterThe J1850 configuration register (Figure 8-17) selects the proper oscillator prescaler, initiates atransmission break for debugging, invokes clock quadrupling operation, and selects the normal-ization bit format.
J_CFG Address:
Reset State: 1F54H
00H
The J1850 configuration (J_CFG) register selects the proper oscilator prescaler, initiates transmission
break for debug, invokes clock quadrupling operation, and selects the normalizartion bit format. This
byte register can be directly addressed through
windowing
. All J1850 bus activity is ignored until you
first write to this register.
7 0
NBF IFR3 4XM TXBRK RXPOL PRE1 PRE0
Bit
Number Bit
Mnemonic Function
7 NBF Normalization Bit Format
This bit specifies which normalization bit (NB) format is to be used.
IFR with CRC Byte IFR without CRC Byte
0 = active long NB 0 = active short NB
1 = active short NB 1 = active long NB
6 IFR3 Type 3 IFR Messaging
This bit selects type 3 IFR messaging, which supports the in-frame transfer
of an unspecified number of data bytes.
0 = normal operation
1 = type 3 IFR messaging
5 4XM Oscillator Quadruple (4x) Mode
This bit allows the J1850 peripheral to operate at four times the normal bit
transfer rate (41.6 Kb/s versus 10.4 Kb/s).
0 = normal operation
1 = 4x mode operation
4 TXBRK Transmission Break
This bit will terminate any transmission in progress by writing a break (BRK)
symbol to the bus.
0 = normal operation
1 = transmit BRK symbol onto bus
3 RXPOL Receive Polarity
This bit changes the polarity of the receive symbol.
0 = normal operation – Rx input inverted
1 = receive polarity enabled – Rx input non-inverted

Figure 8-17. J1850 Configuration (J_CFG) Register