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Intel 87C196CA, 8XC196Jx, 8XC196Kx, 8XC196Lx SUPPLEMENT, Table A-1. 87C196LA Signals Arranged by Functional Categories

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8XC196L

X

SUPPLEMENT

A-2

Table A-1. 87C196LA Signals Arranged by Functional Categories

Addr & Data Input/Output (Cont’d) Program Control Processor Control

Name Pin Name Pin Name Pin Name Pin

AD0 22 P2.1 / RXD 28 AINC# 30 EA# 24

AD1 21 P2.2 29 CPVER 31 EXTINT 29

AD2 20 P2.4 30 PACT# 32 PLLEN 6

AD3 19 P2.6 31 PALE# 28 RESET# 23

AD4 18 P2.7 32 PBUS.0 22 XTAL1 52

AD5 17 P3.0 22 PBUS.1 21 XTAL2 51

AD6 16 P3.1 21 PBUS.2 20

AD7 15 P3.2 20 PBUS.3 19 Bus Cont & Status

AD8 14 P3.3 19 PBUS.4 18 Name Pin

AD9 13 P3.4 18 PBUS.5 17 ADV# / ALE 2

AD10 12 P3.5 17 PBUS.6 16 CLKOUT 32

AD11 11 P3.6 16 PBU S.7 15 RD# 5

AD12 10 P3.7 15 PBUS.8 14 WR# / WRL# 6

AD13 9 P4.0 14 PBUS.9 13

AD14 8 P4.1 13 PBUS.10 12 Power & Ground

AD15 7 P4.2 12 PBUS.11 11 Name Pin

P4.3 11 PBUS.12 10 ANGND 39

Input/Output P4.4 10 PBUS.13 9 VCC 26

Name Pin P4.5 9 PBUS.14 8 VPP 4

P0.2 / ACH2 33 P4.6 8 PBUS.15 7 VREF 40

P0.3 / ACH3 34 P4.7 7 PMODE.0 35 VSS 3

P0.4 / ACH4 35 P5.0 2 PMODE.1 36 VSS1 1

P0.5 / ACH5 36 P5.2 6 PMODE.2 37 VSS1 25

P0.6 / ACH6 37 P5.3 5 PMODE.3 38

P0.7 / ACH7 38 P6.0 / EPA8 / COMP0 45 PROG# 29

P1.0 / EPA0 / T2CLK 44 P6.1 / EPA9 / COMP1 46 PVER 27

P1.1 / EPA1 43 P6.4 / SC0 47

P1.2 / EPA2 / T2DIR 4 2 P6.5 / SD0 48

P1.3 / EPA3 41 P6.6 / SC1 49

P2.0 / TXD 27 P6.7 / SD1 50

Contents

Main Page Page Page Page FIGURES Page TABL ES Page Page CHAPTER 1 GUIDE TO THIS MANUAL Page Page Page CHAPTER 2 ARCHITECTURAL OVERVIEW Page 2-3 ARCHITECTURAL OVERVIEW Figure 2-2. Clock Circuitry (87C196LA, LB Only) F F 2F Page ARCHITECTURAL OVERVIEW Figure 2-4. Effect of Clock Mode on Internal CLKOUT Frequency Table 2-3. Relationships Between Input Frequency, Clock Multiplier, and State Times Page Page Page Page Page CHAPTER 3 ADDRESS SPACE Table 3-1. Address Map SUPPLEMENT NOTE Table 3-1. Address Map (Continued) Figure 3-1. Register File Address Map Table 3-2. Register File Memory Addresses Upper Register File Lower Register File Stack Pointer Address General-purpose Register RAM SUPPLEMENT Table 3-3. 8XC196L Peripheral SFRs Table 3-3. 8XC196L Peripheral SFRs (Continued) SUPPLEMENT Table 3-4. Windows Table 3-4. Windows (Continued) SUPPLEMENT Table 3-4. Windows (Continued) Page Page Page SUPPLEMENT Table 4-1. Interrupt Sources, Vectors, and Priorities Figure 4-1. Interrupt Mask (INT_MASK) Register SUPPLEMENT Figure 4-2. Interrupt Mask 1 (INT_MASK1) Register Figure 4-3. Interrupt Pending (INT_PEND) Register SUPPLEMENT Figure 4-4. Interrupt Pending 1 (INT_PEND1) Register Figure 4-5. PTS Select (PTSSEL) Register SUPPLEMENT Figure 4-6. PTS Service (PTSSRV) Register Page Page CHAPTER 5 I/O PORTS Page 5-3 I/O PORTS Figure 5-1. Ports 1, 2, 5, and 6 Internal Structure (87C196LA, LB Only) Page Page SUPPLEMENT Figure 5-2. Ports 3 and 4 Internal Structure (87C196LA, LB Only) 5-6 Page Page CHAPTER 6 SYNCHRONOUS SERIAL I/O PORT Figure 6-1. SSIO 0 Clock (SSIO0_CLK) Register SUPPLEMENT Figure 6-2. SSIO 1 Clock (SSIO1_CLK) Register SYNCHRONOUS SERIAL I/O PORT Figure 6-2. SSIO 1 Clock (SSIO1_CLK) Register (Continued) Page Page Page CHAPTER 7 EVENT PROCESSOR ARRAY SUPPLEMENT Figure 7-1. EPA Block Diagram (87C196LA, LB Only) 7-2 7-3 EVENT PROCESSOR ARRAY Figure 7-2. EPA Block Diagram (83C196LD Only) SUPPLEMENT Figure 7-4. EPA Interrupt Mask 1 (EPA_MASK1) Register Figure 7-3. EPA Interrupt Mask (EPA_MASK) Register EVENT PROCESSOR ARRAY Figure 7-6. EPA Interrupt Pending 1 (EPA_PEND1) Register Figure 7-5. EPA Interrupt Pending (EPA_PEND) Register SUPPLEMENT Page Page CHAPTER 8 J1850 COMMUNICATIONS CONTROLLER SUPPLEMENT 8-2 Figure 8-2. J1850 Communications Controller Block Diagram Peripheral Data Bus Table 8-1. J1850 Controller Signals Table 8-2. Control and Status Registers Page Page Page Page Page Page Page Figure 8-8. Definition for Start and End of Frame Symbols Table 8-4 details the symbol timing characteristics supported by the 87C196LB. Table 8-4. Huntzicker Symbol Timing Characteristics Page 8-13 Figure 8-10. IFR Type 2 Message Frame 8.4.2.3 IFR Messaging Type 3: Multiple Bytes, Single Responder . . . . . . . . . . Figure 8-11. IFR Type 3 Message Frame Page Page Page Figure 8-16. J1850 Command (J_CMD) Register SUPPLEMENT Figure 8-17. J1850 Configuration (J_CFG) Register J1850 COMMUNICATIONS CONTROLLER Figure 8-17. J1850 Configuration (J_CFG) Register (Continued) SUPPLEMENT Figure 8-18. J1850 Delay (J_DLY) Register Figure 8-19. J1850 Status (J_STAT) Register SUPPLEMENT Figure 8-19. J1850 Status (J_STAT) Register (Continued) Page Page CHAPTER 9 MINIMUM HARDWARE CONSIDERATIONS Page Page Page Page 8XC196L SUPPLEMENT F 2F 10-2 Page Page Page Page CHAPTER 11 PROGRAMMING THE NONVOLATILE MEMORY SUPPLEMENT Table 11-2. 87C196LA, LB OTPROM Address Map 11-3 PROGRAMMING THE NONVOLATILE MEMORY 10 EA# dynamic failure analysis of the device is impossible. Figure 11-1. Slave Programming Circuit Table 11-3. Slave Programming Mode Address Map SUPPLEMENT Figure 11-2. Serial Port Programming Circuit Page Page Page Page Page SUPPLEMENT Table A-1. 87C196LA Signals Arranged by Functional Categories Figure A-1. 87C196LA 52-pin PLCC Package A3419-03 A-3 xx87C196LA20 View of component as mounted on PC board SUPPLEMENT Table A-2. 87C196LB Signals Arranged by Functional Categories Figure A-2. 87C196LB 52-pin PLCC Package A3361-03 A-5 xx87C196LB20 View of component as mounted on PC board SUPPLEMENT Table A-3. 83C196LD Signals Arranged by Functional Categories A-7 Figure A-3. 83C196LD 52-pin PLCC Package Table A-4. Definition of Status Symbols xx83C196LD View of component as mounted on PC board SUPPLEMENT Table A-5. 87C196LA, LB Default Signal Conditions Table A-6. 83C196LD Default Signal Conditions Page Page Page GLOSSARY Page Page Page Page Page Page Page Page Page Page Page Page Page INDEX A B C D P R S U W