Intel 87C196CA, 8XC196Jx, 8XC196Kx, 8XC196Lx - page 92

8XC196L

X

SUPPLEMENT

9-2

9.2 DESIGN CONSIDERATIONS FOR 8XC196LA, LB, AND LD

With the exception of a few new multiplexed functions, the 8XC196Lx microcontrollers are pin

compatible with the 8XC196Jx microcontrollers. The 8XC196J x microcontrollers are 52-lead

versions of 8XC196Kx microcontrollers.

Follow these recommendations to help maintain hardware and software compatibility between

the 8XC196Lx, 8XC196Kx, and future microcontrollers.

•Bus width. Since the 8XC196Lx has neither a WRH# nor a BUSWIDTH pin, the

microcontroller cannot dynamically switch between 8- and 16-bit bus widths. Program the

CCBs to select 8-bit bus mode.

•Wait st ates. Since the 8XC196Lx has no READY pin, the microcontroller cannot rely on a

READY signal to control wait states. Program the CCBs to limit the number of wait states

(0, 1, 2, or 3).

•EPA6–EPA7. These functions exist in the 8XC196Lx, but the associated pins are omitted.

You can use these functions as software timers, to start A/D conversions (on 87C196LA

and LB only), or to reset the timers.

•Slave port. Since the 8XC196Lx has no P5.1/SLPCS and P5.4/SLPINT pins, you cannot

use the slave port.

•ONCE mode. On the 8XC196Lx, the ONCE mode entry function is multiplexed with P2.6

(and TXJ1850 on the 87C196LB) rather than with P5.4 as it is on the 8XC196Kx

(P5.4/SLPINT/ONCE).

��NMI. Since the 8XC196Lx has no NMI pin, the nonmaskable interrupt is not supported.

Initialize the NMI vector (at location 203EH) to point to a RET instruction. This method

provides glitch protection only.

•I/O ports. The following port pins do not exist in the 8XC196Lx: P0.0–P0.1, P1.4–P1.7,

P2.3 and P2.5, P5.1 and P5.4–P5.7, P6.2 and P6.3. Software can still read and write the

associated Px_REG, Px_MODE, and Px_DIR registers. Configure the registers for the

omitted pins as follows:

— Clear the corresponding Px_DIR bits. (Configures pins as complementary outputs.)

— Clear the corresponding Px_MODE bits. (Selects I/O port function.)

— Write either “0” or “1” to the corresponding Px_REG bits. (Effectively ties signals low

or high.)

Do not use the bits associated with the omitted port pins for conditional branch instructions.

Treat these bits as reserved.

•Auto programming. During auto programming, the 8XC196Lx supports only a 16-bit,

zero-wait-state bus configuration.

Contents

Main Page Page Page Page FIGURES Page TABL ES Page Page CHAPTER 1 GUIDE TO THIS MANUAL Page Page Page CHAPTER 2 ARCHITECTURAL OVERVIEW Page 2-3 ARCHITECTURAL OVERVIEW Figure 2-2. Clock Circuitry (87C196LA, LB Only) F F 2F Page ARCHITECTURAL OVERVIEW Figure 2-4. Effect of Clock Mode on Internal CLKOUT Frequency Table 2-3. Relationships Between Input Frequency, Clock Multiplier, and State Times Page Page Page Page Page CHAPTER 3 ADDRESS SPACE Table 3-1. Address Map SUPPLEMENT NOTE Table 3-1. Address Map (Continued) Figure 3-1. Register File Address Map Table 3-2. Register File Memory Addresses Upper Register File Lower Register File Stack Pointer Address General-purpose Register RAM SUPPLEMENT Table 3-3. 8XC196L Peripheral SFRs Table 3-3. 8XC196L Peripheral SFRs (Continued) SUPPLEMENT Table 3-4. Windows Table 3-4. Windows (Continued) SUPPLEMENT Table 3-4. Windows (Continued) Page Page Page SUPPLEMENT Table 4-1. Interrupt Sources, Vectors, and Priorities Figure 4-1. Interrupt Mask (INT_MASK) Register SUPPLEMENT Figure 4-2. Interrupt Mask 1 (INT_MASK1) Register Figure 4-3. Interrupt Pending (INT_PEND) Register SUPPLEMENT Figure 4-4. Interrupt Pending 1 (INT_PEND1) Register Figure 4-5. PTS Select (PTSSEL) Register SUPPLEMENT Figure 4-6. PTS Service (PTSSRV) Register Page Page CHAPTER 5 I/O PORTS Page 5-3 I/O PORTS Figure 5-1. Ports 1, 2, 5, and 6 Internal Structure (87C196LA, LB Only) Page Page SUPPLEMENT Figure 5-2. Ports 3 and 4 Internal Structure (87C196LA, LB Only) 5-6 Page Page CHAPTER 6 SYNCHRONOUS SERIAL I/O PORT Figure 6-1. SSIO 0 Clock (SSIO0_CLK) Register SUPPLEMENT Figure 6-2. SSIO 1 Clock (SSIO1_CLK) Register SYNCHRONOUS SERIAL I/O PORT Figure 6-2. SSIO 1 Clock (SSIO1_CLK) Register (Continued) Page Page Page CHAPTER 7 EVENT PROCESSOR ARRAY SUPPLEMENT Figure 7-1. EPA Block Diagram (87C196LA, LB Only) 7-2 7-3 EVENT PROCESSOR ARRAY Figure 7-2. EPA Block Diagram (83C196LD Only) SUPPLEMENT Figure 7-4. EPA Interrupt Mask 1 (EPA_MASK1) Register Figure 7-3. EPA Interrupt Mask (EPA_MASK) Register EVENT PROCESSOR ARRAY Figure 7-6. EPA Interrupt Pending 1 (EPA_PEND1) Register Figure 7-5. EPA Interrupt Pending (EPA_PEND) Register SUPPLEMENT Page Page CHAPTER 8 J1850 COMMUNICATIONS CONTROLLER SUPPLEMENT 8-2 Figure 8-2. J1850 Communications Controller Block Diagram Peripheral Data Bus Table 8-1. J1850 Controller Signals Table 8-2. Control and Status Registers Page Page Page Page Page Page Page Figure 8-8. Definition for Start and End of Frame Symbols Table 8-4 details the symbol timing characteristics supported by the 87C196LB. Table 8-4. Huntzicker Symbol Timing Characteristics Page 8-13 Figure 8-10. IFR Type 2 Message Frame 8.4.2.3 IFR Messaging Type 3: Multiple Bytes, Single Responder . . . . . . . . . . Figure 8-11. IFR Type 3 Message Frame Page Page Page Figure 8-16. J1850 Command (J_CMD) Register SUPPLEMENT Figure 8-17. J1850 Configuration (J_CFG) Register J1850 COMMUNICATIONS CONTROLLER Figure 8-17. J1850 Configuration (J_CFG) Register (Continued) SUPPLEMENT Figure 8-18. J1850 Delay (J_DLY) Register Figure 8-19. J1850 Status (J_STAT) Register SUPPLEMENT Figure 8-19. J1850 Status (J_STAT) Register (Continued) Page Page CHAPTER 9 MINIMUM HARDWARE CONSIDERATIONS Page Page Page Page 8XC196L SUPPLEMENT F 2F 10-2 Page Page Page Page CHAPTER 11 PROGRAMMING THE NONVOLATILE MEMORY SUPPLEMENT Table 11-2. 87C196LA, LB OTPROM Address Map 11-3 PROGRAMMING THE NONVOLATILE MEMORY 10 EA# dynamic failure analysis of the device is impossible. Figure 11-1. Slave Programming Circuit Table 11-3. Slave Programming Mode Address Map SUPPLEMENT Figure 11-2. Serial Port Programming Circuit Page Page Page Page Page SUPPLEMENT Table A-1. 87C196LA Signals Arranged by Functional Categories Figure A-1. 87C196LA 52-pin PLCC Package A3419-03 A-3 xx87C196LA20 View of component as mounted on PC board SUPPLEMENT Table A-2. 87C196LB Signals Arranged by Functional Categories Figure A-2. 87C196LB 52-pin PLCC Package A3361-03 A-5 xx87C196LB20 View of component as mounted on PC board SUPPLEMENT Table A-3. 83C196LD Signals Arranged by Functional Categories A-7 Figure A-3. 83C196LD 52-pin PLCC Package Table A-4. Definition of Status Symbols xx83C196LD View of component as mounted on PC board SUPPLEMENT Table A-5. 87C196LA, LB Default Signal Conditions Table A-6. 83C196LD Default Signal Conditions Page Page Page GLOSSARY Page Page Page Page Page Page Page Page Page Page Page Page Page INDEX A B C D P R S U W