8XC196LX SUPPLEMENT

input signals set SFDIR. Even if a pin is to be used in special-function mode, you must still ini- tialize the pin as an input or output by writing to the port direction register.

Resistor R1 provides ESD protection for the pin. Input signals are buffered. The standard ports use Schmitt-triggered buffers for improved noise immunity. Port 5 uses a standard input buffer because of the high speeds required for bus control functions. The signals are latched into the port pin register sample latch and output onto the internal bus when the port pin register is read.

The falling edge of RESET# turns on transistor Q3, which remains on for about 300 ns, causing the pin to change rapidly to its reset state. The active-low level of RESET# turns on transistor Q4, which weakly holds the pin low. Q4 remains on, weakly holding the pin low, until your software writes to the port mode register.

NOTE

P2.7 is an exception. After reset, P2.7 carries the CLKOUT signal (half the crystal input frequency) rather than being held low. When CLKOUT is selected, it is always a complementary output.

5-2

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Intel 8XC196Kx, 8XC196Jx, 8XC196Lx, 87C196CA user manual 8XC196LX Supplement