Ssio 1 Clock Register, 1FB7H, Chs Dup | Intel 8XC196Kx guide

8XC196LX SUPPLEMENT

For transmissions, SSIO0_CLK determines whether the SSIO shifts out data bits on rising or fall- ing clock edges. For receptions, SSIO0_CLK determines whether the SSIO samples data bits on rising or falling clock edges.

6.2SSIO 1 CLOCK REGISTER

SSIO1_CLK selects the SSIO mode of operation (standard, duplex, or channel-select), enables the channel-select master contention interrupt request, and selects the phase and polarity for the serial clock (SC1) for channels. In standard mode, use this register to configure the serial clock for channel 1.

SSIO1_CLK	Address:	1FB7H
	Reset State:	00H

The SSIO 1 clock (SSIO1_CLK) register selects the SSIO mode of operation (standard, duplex, or channel-select), enables the channel-select master contention interrupt request, and selects the phase and polarity for the serial clock (SC1) for channel 1.

7

—	—	CHS	DUP

0

CONINT	CONPND	PHAS	POLS

	Bit	Bit				Function
	Number	Mnemonic				Function
	Number	Mnemonic

	7:6	—		Reserved; for compatibility with future devices, write zeros to these bits.

	5	CHS		These bits determine the SSIO operating mode.
				CHS DUP
	4	DUP		CHS DUP		standard mode
				0	0	standard mode
				0	1	duplex mode
				1	0	channel-select half-duplex mode (uses SD1 only)
				1	1	channel-select full-duplex mode (uses both SD0 and SD1)

	3	CONINT		Master Contention Interrupt
				For channel-select master operations, the SSIO sets the master
				contention interrupt pending bit (CONPND) when the CHS# pin is
				externally activated. In a system with multiple masters, an external
				master activates the CHS# signal to request control of the serial clock.
				CONINT determines whether the SSIO sets both CONPND and the
				SSIO0 interrupt pending bit or only CONPND when the CHS# pin is
				externally activated.
				0	= SSIO sets only CONPND
				1	= SSIO sets both CONPND and the SSIO0 interrupt pending bit
				This bit is valid for channel-select master operations and ignored for all
				other operations.


			Figure 6-2. SSIO 1 Clock (SSIO1_CLK) Register

6-2

Image 54

Intel 8XC196Kx, 8XC196Jx, 8XC196Lx, 87C196CA Ssio 1 Clock Register, 1FB7H, CHS DUP Conint Conpnd Phas Pols, Chs Dup

Contents

August Page Contents 8XC196LX Supplement Chapter Synchronous Serial I/O Port Programming the J1850 Controller Entering and Exiting Once ModeFunctional Groupings of Signals Default Conditions Internal Timing Figures 11-3 Tables Guide to This Manual Page Manual Contents Chapter Guide to this Manual Related Documents Related Documents Architectural Overview Page Microcontroller Features Features of the 8XC196Lx and 8XC196Kx Product FamiiesChapter Architectural Overview Block Diagram Internal Timing Clock Circuitry 87C196LA, LB Only 12 MHz State Times at Various FrequenciesMHz 16 MHz External Timing PllenMultiplier State Time Internal Peripherals Uprom Programming Values and LocationsCLK1 CLK0 Event Processor Array 1 I/O PortsSynchronous Serial I/O Port 4 J1850 Communications ControllerPage Address Space Page Chapter Address Space Address PartitionsAddress Map Register File 1BFF Address CA,JT,KTJR, KR Peripheral SPECIAL-FUNCTION Registers XC196Lx Peripheral SFRsUSFR1 LA, LB Rstsrc SSIO1CLKSSIO0CLK Jdly Windowing Windows Base Upper Register File CA, JT, JV, KTUpper Register File CA, JT, JV, KT, LA, LB 4BH 0140H25H 0120H 49H 0100H 48H 24H 12H Standard and PTS Interrupts Page Chapter Standard and PTS Interrupts Interrupt SOURCES, VECTORS, and Priorities Interrupt Sources, Vectors, and Priorities Interrupt Controller PTS ServiceInterrupt Registers Interrupt Source Mnemonic Priority Name Bit Function Number Interrupt Mask RegistersIntmask Bit Mnemonic Interrupt Description LA, LD Interrupt Pending RegistersINTMASK1 NMI Extint SSIO1 SSIO0 Interrupt Pending Intpend Register Intpend Peripheral Transaction Server Registers INTPEND1NMI Ptssel BitInterrupt PTS Vector Ptssrv BitsInterrupt Standard Vector Ports Page Microcontroller Ports Chapter PortsI/O Ports Overview EPA, Ssio 8XC196LX Supplement Configuring Ports 1, 2, 5, and 6 Bidirectional Ports Ports 1, 2, 5, and 6 Internal Structure 87C196LA, LB Only For complementary output configurations Special Bidirectional Port Considerations Internal Structure for Ports 3 and 4 ADDRESS/DATA BUS 8XC196L X Supplement Synchronous Serial Port Page Bit Function Chapter Synchronous Serial I/O PortSsio 0 Clock Register For receptions CHS DUP Conint Conpnd Phas Pols Ssio 1 Clock Register1FB7H CHS SSIO1CLK Page Event Processor Array Page EPA Channels Chapter Event Processor ArrayEPA Functional Overview Device Capture/Compare Compare-only EPA Block Diagram 87C196LA, LB Only EPA Block Diagram 83C196LD Only EPA Mask Registers EpamaskEPAMASK1 EPA Pending Registers EpapendEPAPEND1 EPA Interrupt Priority Vector Register Value InterruptEpaipv J1850 Communications Controller Page J1850 Communications Controller J1850 Functional OverviewPLL Clkout J1850 Communications Controller Block Diagram Signal J1850 Controller Signals and RegistersJ1850 Controller Signals Control and Status Registers J1850 Controller Operation Control State MachineCyclic Redundancy Check Generator Error Detection Symbol Synchronization and Timing CircuitryBus Contention Bit Arbitration Clock Prescaler Delay CompensationSymbol Encoding and Decoding Digital Filter Huntzicker Symbol Definition for J1850 Bit Arbitration Example Message Frames Bit Arbitration Example CRC Byte Standard MessagingHeader Normalization Bit 64µS 128µS NB for IFR with CRC NB for IFR without CRC Huntzicker Symbol Timing Characteristics Name Symbol Bus Level TXmin TXnom TXmax RXmin RXmax Units In-frame Response Messaging IFR Messaging Type 1 Single Byte, Single Responder Transmitting and Receiving Messages Transmitting Messages Transmit Byte CPU JTX Jtxbuf Receiving Messages Receive ByteCPU Jrxbuf Programming the J1850 Command Jcmd Register IFR MessagesProgramming the J1850 Controller Auto JcmdAuto IFR Ignore Abort MSG3 MSG2 MSG1 MSG0 MSG30 Operation Purpose NBF Programming the J1850 Configuration Jcfg RegisterNBF IFR3 4XM Txbrk Rxpol PRE1 PRE0 IFR without CRC Byte Programming the J1850 Delay Compensation Jdly Register PRE1 PRE0 18. J1850 Delay Jdly Register Programming the J1850 Status Jstat Register Jstat Msgtx Msgrx Minimum Hardware Considerations Page Identifying the Reset Source Minimum Hardware Considerations Design Considerations for 8XC196LA, LB, and LD Special Operating Modes Page Chapter Special Operating Modes Entering and Exiting Once Mode 10-3 Page Programming Nonvolatile Memory Page Otprom Address MAP Programming the Nonvolatile MemorySignature Word and Programming Voltage Values Signature Word and Programming Voltage Values Address Range Description Hex Slave Programming Circuit and Address MAPC196LA, LB Otprom Address Map CCB1 Description Address Comments Serial Port Programming Circuit and Address MAP Serial Port Programming Circuit A000-FFFFH Serial Port Programming Mode Address MapDescription Address Range Do not addressPage Signal Descriptions Page Appendix a Signal Descriptions Functional Groupings of Signals Table A-1 C196LA Signals Arranged by Functional Categories Signal Descriptions Table A-2 C196LB Signals Arranged by Functional Categories Figure A-2 C196LB 52-pin Plcc Package Input/Output Cont’d Name Pin Table A-3 C196LD Signals Arranged by Functional CategoriesInput Name Pin Bus Control & Status Default Conditions Table A-5 C196LA, LB Default Signal Conditions Port Alternate During RESET# Upon RESET# PowerSignals Functions Table A-6 C196LD Default Signal Conditions Page Glossary Page Glossary ALUBIT Byte DOUBLE-WORD EPAESD FET Integer LSB ISRLONG-INTEGER LSW MSB MSW PIC PIH PLL PSW PTSPtscb QUAD-WORD Ralu SAR SFRSHORT-INTEGER Uart VPW WDTWord Index Page Index Clkout Index-2