Programming the J1850 Status Jstat Register | Intel 87C196CA

J1850 COMMUNICATIONS CONTROLLER

8.6.4Programming the J1850 Status (J_STAT) Register

The J1850 status register (Figure 8-19) provides the current status of the message and the four interrupt sources associated with the J1850 protocol.

J_STAT	Address:	1F53H
	Reset State:	00H

The J1850 status (J_STAT) register provides the current status of the message transfer, the receive and transmit buffers, and the four interrupt sources associated with the J1850 protocol. This byte register can be directly addressed through windowing. You must write to this register before transmitting each message. Reading this register clears all bits except BUS_STAT.

7

IFR_RCV BUS_CONT BUS_STAT BRK_RCV

0

OVR_UNDR MSG_TX MSG_RX J1850BE

Bit	Bit		Function
Number	Mnemonic		Function
Number	Mnemonic

7	IFR_RCV	In-frame Response Received
		This bit indicates whether the IFR byte has been received and is ready to
		be read from the J1850 receiver (J_RX) register.
		0	= no action
		1	= IFR byte received

6	BUS_CONT	J1850 Bus Contention
		This bit indicates whether bus contention has been detected and arbitration
		has been lost.
		0	= no action
		1	= bus contention

5	BUS_STAT	J1850 Bus Status
		This bit indicates whether a transmission or reception is in progress on the
		J1850 bus.
		0	= J1850 bus idle
		1	= J1850 bus busy

4	BRK_RCV	Break Received
		This bit indicates whether a BRK symbol has been detected on the J1850
		bus.
		0	= no action
		1	= BRK symbol detected

3	OVR_UNDR	Receive Overrun/Transmit Underflow Interrupt
		This bit indicates whether a receive buffer overrun (OVR) or transmit buffer
		underflow (UNDR) has occurred. An overrun occurs when a symbol is
		received while both J_RX and JRX_BUF contain unread bytes. An
		underflow occurs when a transmission is attempted while both J_TX and
		JTX_BUF are empty.
		0	= normal operation
		1	= OVR or UNDR detected

Figure 8-19. J1850 Status (J_STAT) Register

8-21

Image 87

Intel 87C196CA, 8XC196Jx, 8XC196Lx, 8XC196Kx user manual Programming the J1850 Status Jstat Register

Contents

August Page Contents 8XC196LX Supplement Chapter Synchronous Serial I/O Port Internal Timing Entering and Exiting Once ModeFunctional Groupings of Signals Default Conditions Programming the J1850 Controller Figures 11-3 Tables Guide to This Manual Page Chapter Guide to this Manual Manual Contents Related Documents Related Documents Architectural Overview Page Microcontroller Features Features of the 8XC196Lx and 8XC196Kx Product FamiiesChapter Architectural Overview Internal Timing Block Diagram Clock Circuitry 87C196LA, LB Only 16 MHz State Times at Various FrequenciesMHz 12 MHz External Timing PllenMultiplier State Time Internal Peripherals Uprom Programming Values and LocationsCLK1 CLK0 4 J1850 Communications Controller 1 I/O PortsSynchronous Serial I/O Port Event Processor ArrayPage Address Space Page Chapter Address Space Address PartitionsAddress Map 1BFF Register File Address CA,JT,KTJR, KR Peripheral SPECIAL-FUNCTION Registers XC196Lx Peripheral SFRsUSFR1 LA, LB Jdly SSIO1CLKSSIO0CLK Rstsrc Windows Windowing Base Upper Register File CA, JT, JV, KTUpper Register File CA, JT, JV, KT, LA, LB 4BH 0140H25H 0120H 49H 0100H 48H 24H 12H Standard and PTS Interrupts Page Interrupt SOURCES, VECTORS, and Priorities Chapter Standard and PTS Interrupts Interrupt Source Mnemonic Priority Name Interrupt Controller PTS ServiceInterrupt Registers Interrupt Sources, Vectors, and Priorities Bit Mnemonic Interrupt Description Interrupt Mask RegistersIntmask Bit Function Number NMI Extint SSIO1 SSIO0 Interrupt Pending RegistersINTMASK1 LA, LD Intpend Interrupt Pending Intpend Register Peripheral Transaction Server Registers INTPEND1NMI Ptssel BitInterrupt PTS Vector Ptssrv BitsInterrupt Standard Vector Ports Page EPA, Ssio Chapter PortsI/O Ports Overview Microcontroller Ports 8XC196LX Supplement Ports 1, 2, 5, and 6 Internal Structure 87C196LA, LB Only Configuring Ports 1, 2, 5, and 6 Bidirectional Ports Special Bidirectional Port Considerations For complementary output configurations Internal Structure for Ports 3 and 4 ADDRESS/DATA BUS 8XC196L X Supplement Synchronous Serial Port Page For receptions Chapter Synchronous Serial I/O PortSsio 0 Clock Register Bit Function CHS Ssio 1 Clock Register1FB7H CHS DUP Conint Conpnd Phas Pols SSIO1CLK Page Event Processor Array Page Device Capture/Compare Compare-only Chapter Event Processor ArrayEPA Functional Overview EPA Channels EPA Block Diagram 87C196LA, LB Only EPA Block Diagram 83C196LD Only EPA Mask Registers EpamaskEPAMASK1 EPA Pending Registers EpapendEPAPEND1 EPA Interrupt Priority Vector Register Value InterruptEpaipv J1850 Communications Controller Page J1850 Communications Controller J1850 Functional OverviewPLL Clkout J1850 Communications Controller Block Diagram Control and Status Registers J1850 Controller Signals and RegistersJ1850 Controller Signals Signal J1850 Controller Operation Control State MachineCyclic Redundancy Check Generator Bit Arbitration Symbol Synchronization and Timing CircuitryBus Contention Error Detection Digital Filter Delay CompensationSymbol Encoding and Decoding Clock Prescaler Bit Arbitration Example Huntzicker Symbol Definition for J1850 Bit Arbitration Example Message Frames Normalization Bit Standard MessagingHeader CRC Byte 64µS 128µS NB for IFR with CRC NB for IFR without CRC Name Symbol Bus Level TXmin TXnom TXmax RXmin RXmax Units Huntzicker Symbol Timing Characteristics IFR Messaging Type 1 Single Byte, Single Responder In-frame Response Messaging Transmitting Messages Transmitting and Receiving Messages CPU JTX Jtxbuf Transmit Byte Receiving Messages Receive ByteCPU Jrxbuf Programming the J1850 Command Jcmd Register IFR MessagesProgramming the J1850 Controller MSG30 Operation Purpose JcmdAuto IFR Ignore Abort MSG3 MSG2 MSG1 MSG0 Auto IFR without CRC Byte Programming the J1850 Configuration Jcfg RegisterNBF IFR3 4XM Txbrk Rxpol PRE1 PRE0 NBF PRE1 PRE0 Programming the J1850 Delay Compensation Jdly Register 18. J1850 Delay Jdly Register Jstat Programming the J1850 Status Jstat Register Msgrx Msgtx Minimum Hardware Considerations Page Minimum Hardware Considerations Identifying the Reset Source Design Considerations for 8XC196LA, LB, and LD Special Operating Modes Page Chapter Special Operating Modes Entering and Exiting Once Mode 10-3 Page Programming Nonvolatile Memory Page Signature Word and Programming Voltage Values Programming the Nonvolatile MemorySignature Word and Programming Voltage Values Otprom Address MAP CCB1 Slave Programming Circuit and Address MAPC196LA, LB Otprom Address Map Address Range Description Hex Description Address Comments Serial Port Programming Circuit Serial Port Programming Circuit and Address MAP Do not address Serial Port Programming Mode Address MapDescription Address Range A000-FFFFHPage Signal Descriptions Page Functional Groupings of Signals Appendix a Signal Descriptions Table A-1 C196LA Signals Arranged by Functional Categories Signal Descriptions Table A-2 C196LB Signals Arranged by Functional Categories Figure A-2 C196LB 52-pin Plcc Package Bus Control & Status Table A-3 C196LD Signals Arranged by Functional CategoriesInput Name Pin Input/Output Cont’d Name Pin Default Conditions Table A-5 C196LA, LB Default Signal Conditions Port Alternate During RESET# Upon RESET# PowerSignals Functions Table A-6 C196LD Default Signal Conditions Page Glossary Page Glossary ALUBIT Byte DOUBLE-WORD EPAESD Integer FET LSW ISRLONG-INTEGER LSB MSW MSB PIC PIH PLL PSW PTSPtscb Ralu QUAD-WORD SAR SFRSHORT-INTEGER Uart VPW WDTWord Index Page Clkout Index Index-2