Chapter Address Space, Address Partitions | Intel 8XC196Lx manual

CHAPTER 3

ADDRESS SPACE

This chapter describes the differences in the address space of the 8XC196Lx from that of the 8XC196Kx.

3.1ADDRESS PARTITIONS

Table 3-1 is an address map of the 8XC196Lx and 8XC196Kx microcontroller family members.

Table 3-1. Address Map

	Device and Hex Address Range
									Addressing
CA	KRJR,	LD	LBLA,		KTJT,		JV	Description	Addressing
CA	KRJR,	LD	LBLA,		KTJT,		JV		Modes



FFFF	FFFF	FFFF	FFFF		FFFF		FFFF	External device (memory	Indirect or
FFFF	FFFF	FFFF	FFFF		FFFF		FFFF	or I/O) connected to	Indirect or
A000	6000	6000	8000		A000		E000	or I/O) connected to	indexed
A000	6000	6000	8000		A000		E000	address/data bus	indexed
								address/data bus
								Program memory
9FFF	5FFF	5FFF	7FFF		9FFF		DFFF	(internal nonvolatile or	Indirect or
2080	2080	2080	2080		2080		2080	external memory); see	indexed
								Note 1
207F	207F	207F	207F		207F		207F	Special-purpose memory	Indirect or
207F	207F	207F	207F		207F		207F	(internal nonvolatile or	Indirect or
2000	2000	2000	2000		2000		2000	(internal nonvolatile or	indexed
2000	2000	2000	2000		2000		2000	external memory)	indexed
								external memory)
1FFF	1FFF	1FFF	1FFF		1FFF		1FFF	Memory-mapped SFRs	Indirect or
1FE0	1FE0	1FE0	1FE0		1FE0		1FE0	Memory-mapped SFRs	indexed
1FE0	1FE0	1FE0	1FE0		1FE0		1FE0		indexed
								Peripheral SFRs	Indirect,
1FDF	1FDF	1FDF	1FDF		1FDF		1FDF	Peripheral SFRs	indexed, or
1FDF	1FDF	1FDF	1FDF		1FDF		1FDF	(Includes J1850 SFRs on	indexed, or
1F00	1F00	1F00	1F00		1F00		1F00	(Includes J1850 SFRs on	windowed
1F00	1F00	1F00	1F00		1F00		1F00	87C196LB)	windowed
								87C196LB)	direct
									direct
									Indirect,
1EFF	—	—	—		—	—	CAN	SFRs	indexed, or
1E00	—	—	—		—	—	CAN	SFRs	windowed
1E00									windowed
									direct
								External device (memory
1DFF	1EFF	1EFF	1EFF		1EFF		1EFF	or I/O) connected to	Indirect or
1DFF	1EFF	1EFF	1EFF		1EFF		1EFF	address/data bus;	Indirect or
1C00	1C00	1C00	0300		1C00		1E00	address/data bus;	indexed
1C00	1C00	1C00	0300		1C00		1E00	(future SFR expansion;	indexed
								(future SFR expansion;
								see Note 2)
									Indirect,
—	—	—	—	—			1DFF	Register RAM	indexed, or
—	—	—	—	—			1C00	Register RAM	windowed
							1C00		windowed
									direct

NOTES:

1.After a reset, the device fetches its first instruction from 2080H.

2.The content or function of these locations may change in future device revisions, in which case a program that relies on a location in this range might not function properly.

3-1

Image 25

Intel 8XC196Lx, 8XC196Jx, 8XC196Kx, 87C196CA user manual Chapter Address Space, Address Partitions, Address Map

Contents

August Page Contents 8XC196LX Supplement Chapter Synchronous Serial I/O Port Functional Groupings of Signals Default Conditions Entering and Exiting Once ModeProgramming the J1850 Controller Internal Timing Figures 11-3 Tables Guide to This Manual Page Chapter Guide to this Manual Manual Contents Related Documents Related Documents Architectural Overview Page Features of the 8XC196Lx and 8XC196Kx Product Famiies Microcontroller FeaturesChapter Architectural Overview Internal Timing Block Diagram Clock Circuitry 87C196LA, LB Only MHz State Times at Various Frequencies12 MHz 16 MHz Pllen External TimingMultiplier State Time Uprom Programming Values and Locations Internal PeripheralsCLK1 CLK0 Synchronous Serial I/O Port 1 I/O PortsEvent Processor Array 4 J1850 Communications ControllerPage Address Space Page Address Partitions Chapter Address SpaceAddress Map 1BFF Register File CA,JT,KT AddressJR, KR XC196Lx Peripheral SFRs Peripheral SPECIAL-FUNCTION RegistersUSFR1 LA, LB SSIO0CLK SSIO1CLKRstsrc Jdly Windows Windowing Upper Register File CA, JT, JV, KT BaseUpper Register File CA, JT, JV, KT, LA, LB 0140H 4BH25H 0120H 49H 0100H 48H 24H 12H Standard and PTS Interrupts Page Interrupt SOURCES, VECTORS, and Priorities Chapter Standard and PTS Interrupts Interrupt Registers Interrupt Controller PTS ServiceInterrupt Sources, Vectors, and Priorities Interrupt Source Mnemonic Priority Name Intmask Interrupt Mask RegistersBit Function Number Bit Mnemonic Interrupt Description INTMASK1 Interrupt Pending RegistersLA, LD NMI Extint SSIO1 SSIO0 Intpend Interrupt Pending Intpend Register INTPEND1 Peripheral Transaction Server RegistersNMI Bit PtsselInterrupt PTS Vector Bits PtssrvInterrupt Standard Vector Ports Page I/O Ports Overview Chapter PortsMicrocontroller Ports EPA, Ssio 8XC196LX Supplement Ports 1, 2, 5, and 6 Internal Structure 87C196LA, LB Only Configuring Ports 1, 2, 5, and 6 Bidirectional Ports Special Bidirectional Port Considerations For complementary output configurations Internal Structure for Ports 3 and 4 ADDRESS/DATA BUS 8XC196L X Supplement Synchronous Serial Port Page Ssio 0 Clock Register Chapter Synchronous Serial I/O PortBit Function For receptions 1FB7H Ssio 1 Clock RegisterCHS DUP Conint Conpnd Phas Pols CHS SSIO1CLK Page Event Processor Array Page EPA Functional Overview Chapter Event Processor ArrayEPA Channels Device Capture/Compare Compare-only EPA Block Diagram 87C196LA, LB Only EPA Block Diagram 83C196LD Only Epamask EPA Mask RegistersEPAMASK1 Epapend EPA Pending RegistersEPAPEND1 Value Interrupt EPA Interrupt Priority Vector RegisterEpaipv J1850 Communications Controller Page J1850 Functional Overview J1850 Communications ControllerPLL Clkout J1850 Communications Controller Block Diagram J1850 Controller Signals J1850 Controller Signals and RegistersSignal Control and Status Registers Control State Machine J1850 Controller OperationCyclic Redundancy Check Generator Bus Contention Symbol Synchronization and Timing CircuitryError Detection Bit Arbitration Symbol Encoding and Decoding Delay CompensationClock Prescaler Digital Filter Bit Arbitration Example Huntzicker Symbol Definition for J1850 Bit Arbitration Example Message Frames Header Standard MessagingCRC Byte Normalization Bit 64µS 128µS NB for IFR with CRC NB for IFR without CRC Name Symbol Bus Level TXmin TXnom TXmax RXmin RXmax Units Huntzicker Symbol Timing Characteristics IFR Messaging Type 1 Single Byte, Single Responder In-frame Response Messaging Transmitting Messages Transmitting and Receiving Messages CPU JTX Jtxbuf Transmit Byte Receive Byte Receiving MessagesCPU Jrxbuf IFR Messages Programming the J1850 Command Jcmd RegisterProgramming the J1850 Controller Auto IFR Ignore Abort MSG3 MSG2 MSG1 MSG0 JcmdAuto MSG30 Operation Purpose NBF IFR3 4XM Txbrk Rxpol PRE1 PRE0 Programming the J1850 Configuration Jcfg RegisterNBF IFR without CRC Byte PRE1 PRE0 Programming the J1850 Delay Compensation Jdly Register 18. J1850 Delay Jdly Register Jstat Programming the J1850 Status Jstat Register Msgrx Msgtx Minimum Hardware Considerations Page Minimum Hardware Considerations Identifying the Reset Source Design Considerations for 8XC196LA, LB, and LD Special Operating Modes Page Chapter Special Operating Modes Entering and Exiting Once Mode 10-3 Page Programming Nonvolatile Memory Page Signature Word and Programming Voltage Values Programming the Nonvolatile MemoryOtprom Address MAP Signature Word and Programming Voltage Values C196LA, LB Otprom Address Map Slave Programming Circuit and Address MAPAddress Range Description Hex CCB1 Description Address Comments Serial Port Programming Circuit Serial Port Programming Circuit and Address MAP Description Address Range Serial Port Programming Mode Address MapA000-FFFFH Do not addressPage Signal Descriptions Page Functional Groupings of Signals Appendix a Signal Descriptions Table A-1 C196LA Signals Arranged by Functional Categories Signal Descriptions Table A-2 C196LB Signals Arranged by Functional Categories Figure A-2 C196LB 52-pin Plcc Package Input Name Pin Table A-3 C196LD Signals Arranged by Functional CategoriesInput/Output Cont’d Name Pin Bus Control & Status Default Conditions Port Alternate During RESET# Upon RESET# Power Table A-5 C196LA, LB Default Signal ConditionsSignals Functions Table A-6 C196LD Default Signal Conditions Page Glossary Page ALU GlossaryBIT Byte EPA DOUBLE-WORDESD Integer FET LONG-INTEGER ISRLSB LSW MSW MSB PIC PIH PLL PTS PSWPtscb Ralu QUAD-WORD SFR SARSHORT-INTEGER Uart WDT VPWWord Index Page Clkout Index Index-2