Interrupt Registers | Intel 8XC196Jx, 8XC196Lx, 8XC196Kx, 87C196CA

8XC196LX SUPPLEMENT

Table 4-1. Interrupt Sources, Vectors, and Priorities

		Interrupt Controller			PTS Service
			Service		PTS Service
			Service
Interrupt Source	Mnemonic
Interrupt Source	Mnemonic			†				Priority
		Name	Vector	Priority	Name		Vector	Priority

Nonmaskable Interrupt	NMI†	INT15	203EH	30	—		—	—
EXTINT Pin	EXTINT	INT14	203CH	14	PTS14		205CH	29
Reserved	—	INT13	203AH	13	PTS13	205AH		28
SIO Receive	RI	INT12	2038H	12	PTS12		2058H	27
SIO Transmit	TI	INT11	2036H	11	PTS11		2056H	26
SSIO Channel 1 Transfer	SSIO1	INT10	2034H	10	PTS10		2054H	25
SSIO Channel 0 Transfer	SSIO0	INT09	2032H	09	PTS09		2052H	24
J1850 Status (LB only)	J1850ST	INT08	2030H	08	PTS08		2050H	23
Reserved (LA, LD)	—	INT08	2030H	08	PTS08	2050H		23
Unimplemented Opcode	—	—	2012H	—	—	—	—
Software TRAP Instruction	—	—	2010H	—	—	—	—
J1850 Receive (LB only)	J1850RX	INT07	200EH	07	PTS07		204EH	22
Reserved (LA, LD)	—	INT07	200EH	07	PTS07	204EH		22
J1850 Transmit (LB only)	J1850TX	INT06	200CH	06	PTS06		204CH	21
Reserved (LA, LD)	—	INT06	200CH	06	PTS06	204CH		21
A/D Conv. Complete (LA, LB)	AD_DONE	INT05	200AH	05	PTS05		204AH	20
Reserved (LD)	—	INT05	200AH	05	PTS05	204AH		20
EPA Capture/Compare 0	EPA0	INT04	2008H	04	PTS04		2048H	19
EPA Capture/Compare 1	EPA1	INT03	2006H	03	PTS03		2046H	18
EPA Capture/Compare 2	EPA2	INT02	2004H	02	PTS02		2044H	17
EPA Capture/Compare 3	EPA3	INT01	2002H	01	PTS01		2042H	16
EPA Capture/Compare 6–9,	EPAx ††	INT00	2000H	00	PTS00		2040H	15
EPA 0–3, 8–9 Overrun,
EPA Compare 0–1††† ,
Timer 1 Overflow, &
Timer 2 Overflow

†The NMI pin is not bonded out on the 8XC196Lx. To protect against glitches, create a dummy interrupt service routine that contains a RET instruction.

††These interrupts are individually prioritized in the EPAIPV register. Read the EPA pending registers (EPA_PEND and EPA_PEND1) to determine which source caused the interrupt.

†††87C196LA, LB only. The 83C196LD has no EPA compare-only channels.

4.2INTERRUPT REGISTERS

This section describes the changes in the interrupt register bit definitions for the 8XC196Lx fam- ily.

4-2

Image 36

Intel 8XC196Jx, 8XC196Lx Interrupt Registers, Interrupt Sources, Vectors, and Priorities, Interrupt Controller PTS Service

Contents

August Page Contents 8XC196LX Supplement Chapter Synchronous Serial I/O Port Entering and Exiting Once Mode Functional Groupings of Signals Default ConditionsProgramming the J1850 Controller Internal Timing Figures 11-3 Tables Guide to This Manual Page Manual Contents Chapter Guide to this Manual Related Documents Related Documents Architectural Overview Page Microcontroller Features Features of the 8XC196Lx and 8XC196Kx Product FamiiesChapter Architectural Overview Block Diagram Internal Timing Clock Circuitry 87C196LA, LB Only State Times at Various Frequencies MHz12 MHz 16 MHz External Timing PllenMultiplier State Time Internal Peripherals Uprom Programming Values and LocationsCLK1 CLK0 1 I/O Ports Synchronous Serial I/O PortEvent Processor Array 4 J1850 Communications ControllerPage Address Space Page Chapter Address Space Address PartitionsAddress Map Register File 1BFF Address CA,JT,KTJR, KR Peripheral SPECIAL-FUNCTION Registers XC196Lx Peripheral SFRsUSFR1 LA, LB SSIO1CLK SSIO0CLKRstsrc Jdly Windowing Windows Base Upper Register File CA, JT, JV, KTUpper Register File CA, JT, JV, KT, LA, LB 4BH 0140H25H 0120H 49H 0100H 48H 24H 12H Standard and PTS Interrupts Page Chapter Standard and PTS Interrupts Interrupt SOURCES, VECTORS, and Priorities Interrupt Controller PTS Service Interrupt RegistersInterrupt Sources, Vectors, and Priorities Interrupt Source Mnemonic Priority Name Interrupt Mask Registers IntmaskBit Function Number Bit Mnemonic Interrupt Description Interrupt Pending Registers INTMASK1LA, LD NMI Extint SSIO1 SSIO0 Interrupt Pending Intpend Register Intpend Peripheral Transaction Server Registers INTPEND1NMI Ptssel BitInterrupt PTS Vector Ptssrv BitsInterrupt Standard Vector Ports Page Chapter Ports I/O Ports OverviewMicrocontroller Ports EPA, Ssio 8XC196LX Supplement Configuring Ports 1, 2, 5, and 6 Bidirectional Ports Ports 1, 2, 5, and 6 Internal Structure 87C196LA, LB Only For complementary output configurations Special Bidirectional Port Considerations Internal Structure for Ports 3 and 4 ADDRESS/DATA BUS 8XC196L X Supplement Synchronous Serial Port Page Chapter Synchronous Serial I/O Port Ssio 0 Clock RegisterBit Function For receptions Ssio 1 Clock Register 1FB7HCHS DUP Conint Conpnd Phas Pols CHS SSIO1CLK Page Event Processor Array Page Chapter Event Processor Array EPA Functional OverviewEPA Channels Device Capture/Compare Compare-only EPA Block Diagram 87C196LA, LB Only EPA Block Diagram 83C196LD Only EPA Mask Registers EpamaskEPAMASK1 EPA Pending Registers EpapendEPAPEND1 EPA Interrupt Priority Vector Register Value InterruptEpaipv J1850 Communications Controller Page J1850 Communications Controller J1850 Functional OverviewPLL Clkout J1850 Communications Controller Block Diagram J1850 Controller Signals and Registers J1850 Controller SignalsSignal Control and Status Registers J1850 Controller Operation Control State MachineCyclic Redundancy Check Generator Symbol Synchronization and Timing Circuitry Bus ContentionError Detection Bit Arbitration Delay Compensation Symbol Encoding and DecodingClock Prescaler Digital Filter Huntzicker Symbol Definition for J1850 Bit Arbitration Example Message Frames Bit Arbitration Example Standard Messaging HeaderCRC Byte Normalization Bit 64µS 128µS NB for IFR with CRC NB for IFR without CRC Huntzicker Symbol Timing Characteristics Name Symbol Bus Level TXmin TXnom TXmax RXmin RXmax Units In-frame Response Messaging IFR Messaging Type 1 Single Byte, Single Responder Transmitting and Receiving Messages Transmitting Messages Transmit Byte CPU JTX Jtxbuf Receiving Messages Receive ByteCPU Jrxbuf Programming the J1850 Command Jcmd Register IFR MessagesProgramming the J1850 Controller Jcmd Auto IFR Ignore Abort MSG3 MSG2 MSG1 MSG0Auto MSG30 Operation Purpose Programming the J1850 Configuration Jcfg Register NBF IFR3 4XM Txbrk Rxpol PRE1 PRE0NBF IFR without CRC Byte Programming the J1850 Delay Compensation Jdly Register PRE1 PRE0 18. J1850 Delay Jdly Register Programming the J1850 Status Jstat Register Jstat Msgtx Msgrx Minimum Hardware Considerations Page Identifying the Reset Source Minimum Hardware Considerations Design Considerations for 8XC196LA, LB, and LD Special Operating Modes Page Chapter Special Operating Modes Entering and Exiting Once Mode 10-3 Page Programming Nonvolatile Memory Page Programming the Nonvolatile Memory Signature Word and Programming Voltage ValuesOtprom Address MAP Signature Word and Programming Voltage Values Slave Programming Circuit and Address MAP C196LA, LB Otprom Address MapAddress Range Description Hex CCB1 Description Address Comments Serial Port Programming Circuit and Address MAP Serial Port Programming Circuit Serial Port Programming Mode Address Map Description Address RangeA000-FFFFH Do not addressPage Signal Descriptions Page Appendix a Signal Descriptions Functional Groupings of Signals Table A-1 C196LA Signals Arranged by Functional Categories Signal Descriptions Table A-2 C196LB Signals Arranged by Functional Categories Figure A-2 C196LB 52-pin Plcc Package Table A-3 C196LD Signals Arranged by Functional Categories Input Name PinInput/Output Cont’d Name Pin Bus Control & Status Default Conditions Table A-5 C196LA, LB Default Signal Conditions Port Alternate During RESET# Upon RESET# PowerSignals Functions Table A-6 C196LD Default Signal Conditions Page Glossary Page Glossary ALUBIT Byte DOUBLE-WORD EPAESD FET Integer ISR LONG-INTEGERLSB LSW MSB MSW PIC PIH PLL PSW PTSPtscb QUAD-WORD Ralu SAR SFRSHORT-INTEGER Uart VPW WDTWord Index Page Index Clkout Index-2