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Intel 87C196CA, 8XC196Jx, 8XC196Kx, 8XC196Lx SUPPLEMENT, Table 4-1. Interrupt Sources, Vectors, and Priorities

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8XC196L

X

SUPPLEMENT

4-2

4.2 INTERRUPT REGISTERSThis section describes the changes in the interrupt register bit definitions for the 8XC196Lx fam-ily.

Table 4-1. Interrupt Sources, Vectors, and Priorities

Interrupt Source Mnemonic

Interrupt Controller

Service PTS Service

Name

Vector

Priority†

Name

Vector

Priority

Nonmaskable Interrupt NMI†INT15 203EH 30 ———

EXTINT Pin EXTINT INT14 203CH 14 PTS14 205CH 29

Reserved — INT13 203AH 13 PTS13 205AH 28

SIO Receive RI INT12 2038H 12 PTS12 2058H 27

SIO Transmit TI INT11 2036H 11 PTS11 2056H 26

SSIO Channel 1 Transfer SSIO1 INT10 2034H 10 PTS10 2054H 25

SSIO Channel 0 Transfer SSIO0 INT09 2032H 09 PTS09 2052H 24

J1850 Status (LB only) J1850ST INT08 2030H 08 PTS08 2050H 23

Reserved (LA, LD) — INT08 2030H 08 PTS08 2050H 23

Unimplemented Opcode — — 2012H — — — —

Software TRAP Instruction — — 2010H — — — —

J1850 Receive (LB only) J1850RX INT07 200EH 07 PTS07 204EH 22

Reserved (LA, LD) — INT07 200EH 07 PTS07 204EH 22

J1850 Transmit (LB only) J1850TX INT06 200CH 06 PTS06 204CH 21

Reserved (LA, LD) — INT06 200CH 06 PTS06 204CH 21

A/D Conv. Complete (LA, LB) AD_DONE INT05 200AH 05 PTS05 204AH 20

Reserved (LD) — INT05 200AH 05 PTS05 204AH 20

EPA Capture/Compare 0 EPA0 INT04 2008H 04 PTS04 2048H 19

EPA Capture/Compare 1 EPA1 INT03 2006H 03 PTS03 2046H 18

EPA Capture/Compare 2 EPA2 INT02 2004H 02 PTS02 2044H 17

EPA Capture/Compare 3 EPA3 INT01 2002H 01 PTS01 2042H 16

EPA Capture/Compare 6–9,

EPA 0–3, 8–9 Overrun,

EPA Compare 0–1†††,

Timer 1 Overflow, &

Timer 2 Overflow

EPA

x

†† INT00 2000H 00 PTS00 2040H 15

†The NMI pin is not bonded out on the 8XC196L

x

. To protect against glitches, create a dummy interrupt

service routine that contains a RET instruction.

†† These interrupts are individually prioritized in the EPAIPV register. Read the EPA pending registers

(EPA_PEND and EPA_PEND1) to determine which source caused the interrupt.

††† 87C196LA, LB only. The 83C196LD has no EPA compare-only channels.

Contents

Main Page Page Page Page FIGURES Page TABL ES Page Page CHAPTER 1 GUIDE TO THIS MANUAL Page Page Page CHAPTER 2 ARCHITECTURAL OVERVIEW Page 2-3 ARCHITECTURAL OVERVIEW Figure 2-2. Clock Circuitry (87C196LA, LB Only) F F 2F Page ARCHITECTURAL OVERVIEW Figure 2-4. Effect of Clock Mode on Internal CLKOUT Frequency Table 2-3. Relationships Between Input Frequency, Clock Multiplier, and State Times Page Page Page Page Page CHAPTER 3 ADDRESS SPACE Table 3-1. Address Map SUPPLEMENT NOTE Table 3-1. Address Map (Continued) Figure 3-1. Register File Address Map Table 3-2. Register File Memory Addresses Upper Register File Lower Register File Stack Pointer Address General-purpose Register RAM SUPPLEMENT Table 3-3. 8XC196L Peripheral SFRs Table 3-3. 8XC196L Peripheral SFRs (Continued) SUPPLEMENT Table 3-4. Windows Table 3-4. Windows (Continued) SUPPLEMENT Table 3-4. Windows (Continued) Page Page Page SUPPLEMENT Table 4-1. Interrupt Sources, Vectors, and Priorities Figure 4-1. Interrupt Mask (INT_MASK) Register SUPPLEMENT Figure 4-2. Interrupt Mask 1 (INT_MASK1) Register Figure 4-3. Interrupt Pending (INT_PEND) Register SUPPLEMENT Figure 4-4. Interrupt Pending 1 (INT_PEND1) Register Figure 4-5. PTS Select (PTSSEL) Register SUPPLEMENT Figure 4-6. PTS Service (PTSSRV) Register Page Page CHAPTER 5 I/O PORTS Page 5-3 I/O PORTS Figure 5-1. Ports 1, 2, 5, and 6 Internal Structure (87C196LA, LB Only) Page Page SUPPLEMENT Figure 5-2. Ports 3 and 4 Internal Structure (87C196LA, LB Only) 5-6 Page Page CHAPTER 6 SYNCHRONOUS SERIAL I/O PORT Figure 6-1. SSIO 0 Clock (SSIO0_CLK) Register SUPPLEMENT Figure 6-2. SSIO 1 Clock (SSIO1_CLK) Register SYNCHRONOUS SERIAL I/O PORT Figure 6-2. SSIO 1 Clock (SSIO1_CLK) Register (Continued) Page Page Page CHAPTER 7 EVENT PROCESSOR ARRAY SUPPLEMENT Figure 7-1. EPA Block Diagram (87C196LA, LB Only) 7-2 7-3 EVENT PROCESSOR ARRAY Figure 7-2. EPA Block Diagram (83C196LD Only) SUPPLEMENT Figure 7-4. EPA Interrupt Mask 1 (EPA_MASK1) Register Figure 7-3. EPA Interrupt Mask (EPA_MASK) Register EVENT PROCESSOR ARRAY Figure 7-6. EPA Interrupt Pending 1 (EPA_PEND1) Register Figure 7-5. EPA Interrupt Pending (EPA_PEND) Register SUPPLEMENT Page Page CHAPTER 8 J1850 COMMUNICATIONS CONTROLLER SUPPLEMENT 8-2 Figure 8-2. J1850 Communications Controller Block Diagram Peripheral Data Bus Table 8-1. J1850 Controller Signals Table 8-2. Control and Status Registers Page Page Page Page Page Page Page Figure 8-8. Definition for Start and End of Frame Symbols Table 8-4 details the symbol timing characteristics supported by the 87C196LB. Table 8-4. Huntzicker Symbol Timing Characteristics Page 8-13 Figure 8-10. IFR Type 2 Message Frame 8.4.2.3 IFR Messaging Type 3: Multiple Bytes, Single Responder . . . . . . . . . . Figure 8-11. IFR Type 3 Message Frame Page Page Page Figure 8-16. J1850 Command (J_CMD) Register SUPPLEMENT Figure 8-17. J1850 Configuration (J_CFG) Register J1850 COMMUNICATIONS CONTROLLER Figure 8-17. J1850 Configuration (J_CFG) Register (Continued) SUPPLEMENT Figure 8-18. J1850 Delay (J_DLY) Register Figure 8-19. J1850 Status (J_STAT) Register SUPPLEMENT Figure 8-19. J1850 Status (J_STAT) Register (Continued) Page Page CHAPTER 9 MINIMUM HARDWARE CONSIDERATIONS Page Page Page Page 8XC196L SUPPLEMENT F 2F 10-2 Page Page Page Page CHAPTER 11 PROGRAMMING THE NONVOLATILE MEMORY SUPPLEMENT Table 11-2. 87C196LA, LB OTPROM Address Map 11-3 PROGRAMMING THE NONVOLATILE MEMORY 10 EA# dynamic failure analysis of the device is impossible. Figure 11-1. Slave Programming Circuit Table 11-3. Slave Programming Mode Address Map SUPPLEMENT Figure 11-2. Serial Port Programming Circuit Page Page Page Page Page SUPPLEMENT Table A-1. 87C196LA Signals Arranged by Functional Categories Figure A-1. 87C196LA 52-pin PLCC Package A3419-03 A-3 xx87C196LA20 View of component as mounted on PC board SUPPLEMENT Table A-2. 87C196LB Signals Arranged by Functional Categories Figure A-2. 87C196LB 52-pin PLCC Package A3361-03 A-5 xx87C196LB20 View of component as mounted on PC board SUPPLEMENT Table A-3. 83C196LD Signals Arranged by Functional Categories A-7 Figure A-3. 83C196LD 52-pin PLCC Package Table A-4. Definition of Status Symbols xx83C196LD View of component as mounted on PC board SUPPLEMENT Table A-5. 87C196LA, LB Default Signal Conditions Table A-6. 83C196LD Default Signal Conditions Page Page Page GLOSSARY Page Page Page Page Page Page Page Page Page Page Page Page Page INDEX A B C D P R S U W