ARCHITECTURAL OVERVIEW
2.5.1I/O Ports
The I/O ports of the 8XC196Lx are functionally identical to those of the 8XC196Jx. However, on the 87C196LA and LB the reset state level of all 41
2.5.2Synchronous Serial I/O Port
The synchronous serial I/O (SSIO) port on the 8XC196Lx has been enhanced, implementing two new special function registers (SSIO0_CLK and SSIO1_CLK) that allow you to select the oper- ating mode and configure the phase and polarity of the serial clock signals.
2.5.3Event Processor Array
The 8XC196Lx’s event processor array (EPA) is functionally identical to that of the 8XC196Jx, except that it has only two EPA capture/compare channels without pins instead of four. In addi- tion the LD has no
2.5.4J1850 Communications Controller
The 87C196LB microcontroller has a peripheral not found on the 8XC196Kx microcontrollers or any other Lx microcontroller, the J1850 peripheral. The J1850 communications controller man- ages communications between multiple network nodes. This integrated peripheral supports the
10.4Kb/s VPW (variable
2.6DESIGN CONSIDERATIONS
With the exception of a few new multiplexed functions, the 8XC196Lx microcontrollers are pin compatible with the 8XC196Jx microcontrollers. The 8XC196Jx microcontrollers are