Message Frames, Bit Arbitration Example | Intel 8XC196Kx, 8XC196Jx

8XC196LX SUPPLEMENT

of arbitration, nodes A, C, and D are all transmitting an “active 0” symbol, thus the idle state of the “passive 1” symbol is overruled in favor of the driven state of the “active 0” symbol.

Node C is the next node to discontinue transmitting when it attempts to take control of the bus by transmitting an “active 1” symbol. However, nodes A and D maintain control by continuing to drive the bus with an “active 0” symbol.

Finally, node D discontinues transmitting when its attempt to hold the bus in an idle state is over- ruled by the driven state of the “active 1” symbol on node A. Thus, node A is awarded arbitration.

The busline signal, detected on the bus by the receiver, reflects node A’s message, as this is the only node that did not experience contention.

"0"

"0"

"0"

"0"

"1"

"0"

"0"

"1"

Node A

"0" "0""1"

Node B

Point of

Arbitration

"0"	"0"	"0"	"0"	"1"	"1"	Point of
Node C						Arbitration

"0"

"0"

"0"

"0"

"1"

"0"

"1"

Node D

Point of

Arbitration

Busline

A5223-01

Figure 8-5. Bit Arbitration Example

8.4MESSAGE FRAMES

A message transmission or reception is transferred within a message frame that adds control and error-detection bits to the content of the message. The frame for an IFR message differs slightly from that for a standard message, but they contain similar information (Figure 8-6).

8-8

Image 74

Intel 8XC196Kx, 8XC196Jx, 8XC196Lx, 87C196CA user manual Message Frames, Bit Arbitration Example

Contents

August Page Contents 8XC196LX Supplement Chapter Synchronous Serial I/O Port Programming the J1850 Controller Entering and Exiting Once ModeFunctional Groupings of Signals Default Conditions Internal Timing Figures 11-3 Tables Guide to This Manual Page Manual Contents Chapter Guide to this Manual Related Documents Related Documents Architectural Overview Page Chapter Architectural Overview Microcontroller FeaturesFeatures of the 8XC196Lx and 8XC196Kx Product Famiies Block Diagram Internal Timing Clock Circuitry 87C196LA, LB Only 12 MHz State Times at Various FrequenciesMHz 16 MHz Multiplier State Time External TimingPllen CLK1 CLK0 Internal PeripheralsUprom Programming Values and Locations Event Processor Array 1 I/O PortsSynchronous Serial I/O Port 4 J1850 Communications ControllerPage Address Space Page Address Map Chapter Address SpaceAddress Partitions Register File 1BFF JR, KR AddressCA,JT,KT USFR1 LA, LB Peripheral SPECIAL-FUNCTION RegistersXC196Lx Peripheral SFRs Rstsrc SSIO1CLKSSIO0CLK Jdly Windowing Windows Upper Register File CA, JT, JV, KT, LA, LB BaseUpper Register File CA, JT, JV, KT 25H 0120H 49H 0100H 48H 24H 12H 4BH0140H Standard and PTS Interrupts Page Chapter Standard and PTS Interrupts Interrupt SOURCES, VECTORS, and Priorities Interrupt Sources, Vectors, and Priorities Interrupt Controller PTS ServiceInterrupt Registers Interrupt Source Mnemonic Priority Name Bit Function Number Interrupt Mask RegistersIntmask Bit Mnemonic Interrupt Description LA, LD Interrupt Pending RegistersINTMASK1 NMI Extint SSIO1 SSIO0 Interrupt Pending Intpend Register Intpend NMI Peripheral Transaction Server RegistersINTPEND1 Interrupt PTS Vector PtsselBit Interrupt Standard Vector PtssrvBits Ports Page Microcontroller Ports Chapter PortsI/O Ports Overview EPA, Ssio 8XC196LX Supplement Configuring Ports 1, 2, 5, and 6 Bidirectional Ports Ports 1, 2, 5, and 6 Internal Structure 87C196LA, LB Only For complementary output configurations Special Bidirectional Port Considerations Internal Structure for Ports 3 and 4 ADDRESS/DATA BUS 8XC196L X Supplement Synchronous Serial Port Page Bit Function Chapter Synchronous Serial I/O PortSsio 0 Clock Register For receptions CHS DUP Conint Conpnd Phas Pols Ssio 1 Clock Register1FB7H CHS SSIO1CLK Page Event Processor Array Page EPA Channels Chapter Event Processor ArrayEPA Functional Overview Device Capture/Compare Compare-only EPA Block Diagram 87C196LA, LB Only EPA Block Diagram 83C196LD Only EPAMASK1 EPA Mask RegistersEpamask EPAPEND1 EPA Pending RegistersEpapend Epaipv EPA Interrupt Priority Vector RegisterValue Interrupt J1850 Communications Controller Page PLL Clkout J1850 Communications ControllerJ1850 Functional Overview J1850 Communications Controller Block Diagram Signal J1850 Controller Signals and RegistersJ1850 Controller Signals Control and Status Registers Cyclic Redundancy Check Generator J1850 Controller OperationControl State Machine Error Detection Symbol Synchronization and Timing CircuitryBus Contention Bit Arbitration Clock Prescaler Delay CompensationSymbol Encoding and Decoding Digital Filter Huntzicker Symbol Definition for J1850 Bit Arbitration Example Message Frames Bit Arbitration Example CRC Byte Standard MessagingHeader Normalization Bit 64µS 128µS NB for IFR with CRC NB for IFR without CRC Huntzicker Symbol Timing Characteristics Name Symbol Bus Level TXmin TXnom TXmax RXmin RXmax Units In-frame Response Messaging IFR Messaging Type 1 Single Byte, Single Responder Transmitting and Receiving Messages Transmitting Messages Transmit Byte CPU JTX Jtxbuf CPU Jrxbuf Receiving MessagesReceive Byte Programming the J1850 Controller Programming the J1850 Command Jcmd RegisterIFR Messages Auto JcmdAuto IFR Ignore Abort MSG3 MSG2 MSG1 MSG0 MSG30 Operation Purpose NBF Programming the J1850 Configuration Jcfg RegisterNBF IFR3 4XM Txbrk Rxpol PRE1 PRE0 IFR without CRC Byte Programming the J1850 Delay Compensation Jdly Register PRE1 PRE0 18. J1850 Delay Jdly Register Programming the J1850 Status Jstat Register Jstat Msgtx Msgrx Minimum Hardware Considerations Page Identifying the Reset Source Minimum Hardware Considerations Design Considerations for 8XC196LA, LB, and LD Special Operating Modes Page Chapter Special Operating Modes Entering and Exiting Once Mode 10-3 Page Programming Nonvolatile Memory Page Otprom Address MAP Programming the Nonvolatile MemorySignature Word and Programming Voltage Values Signature Word and Programming Voltage Values Address Range Description Hex Slave Programming Circuit and Address MAPC196LA, LB Otprom Address Map CCB1 Description Address Comments Serial Port Programming Circuit and Address MAP Serial Port Programming Circuit A000-FFFFH Serial Port Programming Mode Address MapDescription Address Range Do not addressPage Signal Descriptions Page Appendix a Signal Descriptions Functional Groupings of Signals Table A-1 C196LA Signals Arranged by Functional Categories Signal Descriptions Table A-2 C196LB Signals Arranged by Functional Categories Figure A-2 C196LB 52-pin Plcc Package Input/Output Cont’d Name Pin Table A-3 C196LD Signals Arranged by Functional CategoriesInput Name Pin Bus Control & Status Default Conditions Signals Functions Table A-5 C196LA, LB Default Signal ConditionsPort Alternate During RESET# Upon RESET# Power Table A-6 C196LD Default Signal Conditions Page Glossary Page BIT GlossaryALU Byte ESD DOUBLE-WORDEPA FET Integer LSB ISRLONG-INTEGER LSW MSB MSW PIC PIH PLL Ptscb PSWPTS QUAD-WORD Ralu SHORT-INTEGER SARSFR Uart Word VPWWDT Index Page Index Clkout Index-2