Intel 87C196CA Symbol Synchronization and Timing Circuitry, Bus Contention, Bit Arbitration

J1850 COMMUNICATIONS CONTROLLER

8.3.1.2Bus Contention

Bus contention arises when multiple nodes attempt to access and transmit message frames across the J1850 bus simultaneously. This creates a conflict on the bus. The recognition of conflicting symbols or bits on the bus is referred to as contention detection. For example, if a node observes a difference between a symbol it transmits to the J1850 bus and the symbol that it detects on the bus, that node has detected contention to the transmission of its message frame. Only one message frame from one node vying for the bus wins arbitration on each symbol or bit of its frame. This winning message frame does not experience or detect contention. The message frames that were not awarded arbitration will experience contention.

8.3.1.3Bit Arbitration

A bit arbitration scheme is used to resolve such conflicts as bus contention. The J1850 protocol uses the carrier sense multiple access (CSMA) bit arbitration scheme. Bit arbitration is the pro- cess of settling conflicts that occur when multiple nodes attempt to transmit one bit or symbol at a time across a single bus. A symbol is simply a timing-level formatted bit. By definition, a node that detects contention has lost arbitration and will discontinue transmitting any further symbols remaining in its message frame. Remaining nodes vying for the bus will continue to send their symbols until the next instance of contention is detected or arbitration is awarded. This process continues until a complete message frame from one node has been transmitted. For details on this arbitration scheme, refer to the “Bit Arbitration Example” on page 8-7.

8.3.1.4Error Detection

The J1850 controller’s error detection logic monitors the bus for four error conditions, and sets the J1850BE interrupt pending bit in the J_STAT register if an error occurs. The following list describes each error type:

•CRC error — the calculated CRC checksum received on incoming messages has a value other than C4H (the expected value for all received message frames).

•bus symbol timing error — the symbol stream on the J1850 bus contains an invalid symbol. An invalid symbol is any signal that is between 8 µs and 34 µs in duration.

•incomplete byte error — an EOD/EOF symbol occurred,but was not on a byte boundary; the number of bits recieved was not a multiple of eight.

•no echo — the message is transmitted; however, the transmission’s echo back through the feedback loop to the receiver has not been detected within the allowable 60 µs window.

8.3.2Symbol Synchronization and Timing Circuitry

The symbol synchronization and timing (SST) circuitry consists of a clock prescaler, digital filter, delay compensation circuitry, and synchronization and symbol encoding/decoding circuitry. The SST supports Huntzicker encoding of symbols, which entails 10.4 Kb/s variable pulse-width (VPW) operation for valid edge detection on message receptions.

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