Bit Arbitration Example | Intel 8XC196Lx, 8XC196Jx, 8XC196Kx

J1850 COMMUNICATIONS CONTROLLER

1					1			64µS
				128µS

					or
0				"passive 1"	0			"active 1"
0					0

1					1			128µS
				64µS

					or
0				"passive 0"	0			"active 0"
0					0

A5219-01

Figure 8-3. Huntzicker Symbol Definition for J1850

A symbol is defined as a timing-level formatted bit. The VPW symbol timing requirements stip- ulate that there is one symbol per transition and one transition per symbol. This ensures that a message frame will always result in a uniform square waveform of varying level durations. Fig- ure 8-4 depicts a typical Huntzicker formatted data byte of hex value CCH.

"1"	"1"	"0"	"0"	"1"	"1"	"0"	"0"
B7	B6	B5	B4	B3	B2	B1	B0

A5222-01

Figure 8-4. Typical VPW Waveform

Bits 7 and 3 carry logic level 1 data; however, they are represented by a passive-level symbol in keeping with the VPW requirements. Bits 4 and 0 carry logic level 0 data and are represented by an active-level symbol.

8.3.3Bit Arbitration Example

The drive capacity of each symbol establishes the priority for arbitration. By definition, an active bus level is a driven state, and a passive bus level is a non-driven, or idle, state. A driven bus state is always given priority over an idle bus in arbitration. An “active 0” state has priority over an “active 1” state in arbitration, because the “active 0” state is driven over a longer duration, 128 µs versus the “active 1” state’s drive time of 64 µs. Similarly, a “passive 0” state has priority over

a “passive 1” state, because the “passive 0” state comes out of its idle state in a shorter period of time, 64 µs versus the “passive 1” state’s idle time of 128 µs.

For example, Figure 8-5 illustrates four nodes vying for the bus. Node B is the first node to dis- continue transmitting when it attempts to transmit a “passive 1” symbol onto the bus. At the point

8-7

Image 73

Intel 8XC196Lx, 8XC196Jx, 8XC196Kx, 87C196CA user manual Bit Arbitration Example, Huntzicker Symbol Definition for J1850

Contents

August Page Contents 8XC196LX Supplement Chapter Synchronous Serial I/O Port Functional Groupings of Signals Default Conditions Entering and Exiting Once ModeProgramming the J1850 Controller Internal Timing Figures 11-3 Tables Guide to This Manual Page Chapter Guide to this Manual Manual Contents Related Documents Related Documents Architectural Overview Page Features of the 8XC196Lx and 8XC196Kx Product Famiies Microcontroller FeaturesChapter Architectural Overview Internal Timing Block Diagram Clock Circuitry 87C196LA, LB Only MHz State Times at Various Frequencies12 MHz 16 MHz Pllen External TimingMultiplier State Time Uprom Programming Values and Locations Internal PeripheralsCLK1 CLK0 Synchronous Serial I/O Port 1 I/O PortsEvent Processor Array 4 J1850 Communications ControllerPage Address Space Page Address Partitions Chapter Address SpaceAddress Map 1BFF Register File CA,JT,KT AddressJR, KR XC196Lx Peripheral SFRs Peripheral SPECIAL-FUNCTION RegistersUSFR1 LA, LB SSIO0CLK SSIO1CLKRstsrc Jdly Windows Windowing Upper Register File CA, JT, JV, KT BaseUpper Register File CA, JT, JV, KT, LA, LB 0140H 4BH25H 0120H 49H 0100H 48H 24H 12H Standard and PTS Interrupts Page Interrupt SOURCES, VECTORS, and Priorities Chapter Standard and PTS Interrupts Interrupt Registers Interrupt Controller PTS ServiceInterrupt Sources, Vectors, and Priorities Interrupt Source Mnemonic Priority Name Intmask Interrupt Mask RegistersBit Function Number Bit Mnemonic Interrupt Description INTMASK1 Interrupt Pending RegistersLA, LD NMI Extint SSIO1 SSIO0 Intpend Interrupt Pending Intpend Register INTPEND1 Peripheral Transaction Server RegistersNMI Bit PtsselInterrupt PTS Vector Bits PtssrvInterrupt Standard Vector Ports Page I/O Ports Overview Chapter PortsMicrocontroller Ports EPA, Ssio 8XC196LX Supplement Ports 1, 2, 5, and 6 Internal Structure 87C196LA, LB Only Configuring Ports 1, 2, 5, and 6 Bidirectional Ports Special Bidirectional Port Considerations For complementary output configurations Internal Structure for Ports 3 and 4 ADDRESS/DATA BUS 8XC196L X Supplement Synchronous Serial Port Page Ssio 0 Clock Register Chapter Synchronous Serial I/O PortBit Function For receptions 1FB7H Ssio 1 Clock RegisterCHS DUP Conint Conpnd Phas Pols CHS SSIO1CLK Page Event Processor Array Page EPA Functional Overview Chapter Event Processor ArrayEPA Channels Device Capture/Compare Compare-only EPA Block Diagram 87C196LA, LB Only EPA Block Diagram 83C196LD Only Epamask EPA Mask RegistersEPAMASK1 Epapend EPA Pending RegistersEPAPEND1 Value Interrupt EPA Interrupt Priority Vector RegisterEpaipv J1850 Communications Controller Page J1850 Functional Overview J1850 Communications ControllerPLL Clkout J1850 Communications Controller Block Diagram J1850 Controller Signals J1850 Controller Signals and RegistersSignal Control and Status Registers Control State Machine J1850 Controller OperationCyclic Redundancy Check Generator Bus Contention Symbol Synchronization and Timing CircuitryError Detection Bit Arbitration Symbol Encoding and Decoding Delay CompensationClock Prescaler Digital Filter Bit Arbitration Example Huntzicker Symbol Definition for J1850 Bit Arbitration Example Message Frames Header Standard MessagingCRC Byte Normalization Bit 64µS 128µS NB for IFR with CRC NB for IFR without CRC Name Symbol Bus Level TXmin TXnom TXmax RXmin RXmax Units Huntzicker Symbol Timing Characteristics IFR Messaging Type 1 Single Byte, Single Responder In-frame Response Messaging Transmitting Messages Transmitting and Receiving Messages CPU JTX Jtxbuf Transmit Byte Receive Byte Receiving MessagesCPU Jrxbuf IFR Messages Programming the J1850 Command Jcmd RegisterProgramming the J1850 Controller Auto IFR Ignore Abort MSG3 MSG2 MSG1 MSG0 JcmdAuto MSG30 Operation Purpose NBF IFR3 4XM Txbrk Rxpol PRE1 PRE0 Programming the J1850 Configuration Jcfg RegisterNBF IFR without CRC Byte PRE1 PRE0 Programming the J1850 Delay Compensation Jdly Register 18. J1850 Delay Jdly Register Jstat Programming the J1850 Status Jstat Register Msgrx Msgtx Minimum Hardware Considerations Page Minimum Hardware Considerations Identifying the Reset Source Design Considerations for 8XC196LA, LB, and LD Special Operating Modes Page Chapter Special Operating Modes Entering and Exiting Once Mode 10-3 Page Programming Nonvolatile Memory Page Signature Word and Programming Voltage Values Programming the Nonvolatile MemoryOtprom Address MAP Signature Word and Programming Voltage Values C196LA, LB Otprom Address Map Slave Programming Circuit and Address MAPAddress Range Description Hex CCB1 Description Address Comments Serial Port Programming Circuit Serial Port Programming Circuit and Address MAP Description Address Range Serial Port Programming Mode Address MapA000-FFFFH Do not addressPage Signal Descriptions Page Functional Groupings of Signals Appendix a Signal Descriptions Table A-1 C196LA Signals Arranged by Functional Categories Signal Descriptions Table A-2 C196LB Signals Arranged by Functional Categories Figure A-2 C196LB 52-pin Plcc Package Input Name Pin Table A-3 C196LD Signals Arranged by Functional CategoriesInput/Output Cont’d Name Pin Bus Control & Status Default Conditions Port Alternate During RESET# Upon RESET# Power Table A-5 C196LA, LB Default Signal ConditionsSignals Functions Table A-6 C196LD Default Signal Conditions Page Glossary Page ALU GlossaryBIT Byte EPA DOUBLE-WORDESD Integer FET LONG-INTEGER ISRLSB LSW MSW MSB PIC PIH PLL PTS PSWPtscb Ralu QUAD-WORD SFR SARSHORT-INTEGER Uart WDT VPWWord Index Page Clkout Index Index-2