August
Page
Contents
8XC196LX Supplement Chapter Synchronous Serial I/O Port
Functional Groupings of Signals Default Conditions
Entering and Exiting Once Mode
Programming the J1850 Controller
Internal Timing
Figures
11-3
Tables
Guide to This Manual
Page
Chapter Guide to this Manual
Manual Contents
Related Documents
Related Documents
Architectural Overview
Page
Chapter Architectural Overview
Microcontroller Features
Features of the 8XC196Lx and 8XC196Kx Product Famiies
Internal Timing
Block Diagram
Clock Circuitry 87C196LA, LB Only
MHz
State Times at Various Frequencies
12 MHz
16 MHz
Multiplier State Time
External Timing
Pllen
CLK1 CLK0
Internal Peripherals
Uprom Programming Values and Locations
Synchronous Serial I/O Port
1 I/O Ports
Event Processor Array
4 J1850 Communications Controller
Page
Address Space
Page
Address Map
Chapter Address Space
Address Partitions
1BFF
Register File
JR, KR
Address
CA,JT,KT
USFR1 LA, LB
Peripheral SPECIAL-FUNCTION Registers
XC196Lx Peripheral SFRs
SSIO0CLK
SSIO1CLK
Rstsrc
Jdly
Windows
Windowing
Upper Register File CA, JT, JV, KT, LA, LB
Base
Upper Register File CA, JT, JV, KT
25H 0120H 49H 0100H 48H 24H 12H
4BH
0140H
Standard and PTS Interrupts
Page
Interrupt SOURCES, VECTORS, and Priorities
Chapter Standard and PTS Interrupts
Interrupt Registers
Interrupt Controller PTS Service
Interrupt Sources, Vectors, and Priorities
Interrupt Source Mnemonic Priority Name
Intmask
Interrupt Mask Registers
Bit Function Number
Bit Mnemonic Interrupt Description
INTMASK1
Interrupt Pending Registers
LA, LD
NMI Extint SSIO1 SSIO0
Intpend
Interrupt Pending Intpend Register
NMI
Peripheral Transaction Server Registers
INTPEND1
Interrupt PTS Vector
Ptssel
Bit
Interrupt Standard Vector
Ptssrv
Bits
Ports
Page
I/O Ports Overview
Chapter Ports
Microcontroller Ports
EPA, Ssio
8XC196LX Supplement
Ports 1, 2, 5, and 6 Internal Structure 87C196LA, LB Only
Configuring Ports 1, 2, 5, and 6 Bidirectional Ports
Special Bidirectional Port Considerations
For complementary output configurations
Internal Structure for Ports 3 and 4 ADDRESS/DATA BUS
8XC196L X Supplement
Synchronous Serial Port
Page
Ssio 0 Clock Register
Chapter Synchronous Serial I/O Port
Bit Function
For receptions
1FB7H
Ssio 1 Clock Register
CHS DUP Conint Conpnd Phas Pols
CHS
SSIO1CLK
Page
Event Processor Array
Page
EPA Functional Overview
Chapter Event Processor Array
EPA Channels
Device Capture/Compare Compare-only
EPA Block Diagram 87C196LA, LB Only
EPA Block Diagram 83C196LD Only
EPAMASK1
EPA Mask Registers
Epamask
EPAPEND1
EPA Pending Registers
Epapend
Epaipv
EPA Interrupt Priority Vector Register
Value Interrupt
J1850 Communications Controller
Page
PLL Clkout
J1850 Communications Controller
J1850 Functional Overview
J1850 Communications Controller Block Diagram
J1850 Controller Signals
J1850 Controller Signals and Registers
Signal
Control and Status Registers
Cyclic Redundancy Check Generator
J1850 Controller Operation
Control State Machine
Bus Contention
Symbol Synchronization and Timing Circuitry
Error Detection
Bit Arbitration
Symbol Encoding and Decoding
Delay Compensation
Clock Prescaler
Digital Filter
Bit Arbitration Example
Huntzicker Symbol Definition for J1850
Bit Arbitration Example
Message Frames
Header
Standard Messaging
CRC Byte
Normalization Bit
64µS 128µS NB for IFR with CRC NB for IFR without CRC
Name Symbol Bus Level TXmin TXnom TXmax RXmin RXmax Units
Huntzicker Symbol Timing Characteristics
IFR Messaging Type 1 Single Byte, Single Responder
In-frame Response Messaging
Transmitting Messages
Transmitting and Receiving Messages
CPU JTX Jtxbuf
Transmit Byte
CPU Jrxbuf
Receiving Messages
Receive Byte
Programming the J1850 Controller
Programming the J1850 Command Jcmd Register
IFR Messages
Auto IFR Ignore Abort MSG3 MSG2 MSG1 MSG0
Jcmd
Auto
MSG30 Operation Purpose
NBF IFR3 4XM Txbrk Rxpol PRE1 PRE0
Programming the J1850 Configuration Jcfg Register
NBF
IFR without CRC Byte
PRE1 PRE0
Programming the J1850 Delay Compensation Jdly Register
18. J1850 Delay Jdly Register
Jstat
Programming the J1850 Status Jstat Register
Msgrx
Msgtx
Minimum Hardware Considerations
Page
Minimum Hardware Considerations
Identifying the Reset Source
Design Considerations for 8XC196LA, LB, and LD
Special Operating Modes
Page
Chapter Special Operating Modes
Entering and Exiting Once Mode
10-3
Page
Programming Nonvolatile Memory
Page
Signature Word and Programming Voltage Values
Programming the Nonvolatile Memory
Otprom Address MAP
Signature Word and Programming Voltage Values
C196LA, LB Otprom Address Map
Slave Programming Circuit and Address MAP
Address Range Description Hex
CCB1
Description Address Comments
Serial Port Programming Circuit
Serial Port Programming Circuit and Address MAP
Description Address Range
Serial Port Programming Mode Address Map
A000-FFFFH
Do not address
Page
Signal Descriptions
Page
Functional Groupings of Signals
Appendix a Signal Descriptions
Table A-1 C196LA Signals Arranged by Functional Categories
Signal Descriptions
Table A-2 C196LB Signals Arranged by Functional Categories
Figure A-2 C196LB 52-pin Plcc Package
Input Name Pin
Table A-3 C196LD Signals Arranged by Functional Categories
Input/Output Cont’d Name Pin
Bus Control & Status
Default Conditions
Signals Functions
Table A-5 C196LA, LB Default Signal Conditions
Port Alternate During RESET# Upon RESET# Power
Table A-6 C196LD Default Signal Conditions
Page
Glossary
Page
BIT
Glossary
ALU
Byte
ESD
DOUBLE-WORD
EPA
Integer
FET
LONG-INTEGER
ISR
LSB
LSW
MSW
MSB
PIC PIH PLL
Ptscb
PSW
PTS
Ralu
QUAD-WORD
SHORT-INTEGER
SAR
SFR
Uart
Word
VPW
WDT
Index
Page
Clkout
Index
Index-2