Intel 8XC196Lx, 8XC196Jx, 8XC196Kx, 87C196CA user manual Clock Circuitry 87C196LA, LB Only

ARCHITECTURAL OVERVIEW

			Disable
			PLL
			(Powerdown)
FXTAL1
XTAL1
	XTAL1	XTAL1	PLLEN
XTAL2
Disable Oscillator	F	2F	1
(Powerdown)			0
			f
			Divide by two
			Circuit

Phase	Filter
Comparator

Phase-locked

Oscillator

Phase-locked Loop

Clock Multiplier

Disable Clock Input (Powerdown)

f/2

Clock

Generators

f/2

Programmable

Divider

(CLK1:0)

Clock

Failure

Detection

To reset logic

Disable Clocks (Idle, Powerdown) CPU Clocks (PH1, PH2)

Peripheral Clocks (PH1, PH2)

OSC

0

CLKOUT

1

Disable Clocks (Powerdown)

A5290-01

Figure 2-2. Clock Circuitry (87C196LA, LB Only)

The rising edges of PH1 and PH2 generate the internal CLKOUT signal (Figure 2-3). The clock circuitry routes separate internal clock signals to the CPU and the peripherals to provide flexibil- ity in power management. It also outputs the CLKOUT signal on the CLKOUT pin. Because of the complex logic in the clock circuitry, the signal on the CLKOUT pin is a delayed version of the internal CLKOUT signal. This delay varies with temperature and voltage.

2-3