P
Period (t), 2-4 Port 0
idle, powerdown, reset status, A-8, A-9 overview, 5-1
Port 1 configuring, 5-3
idle, powerdown, reset status, A-8, A-9 overview, 5-1
Port 2 configuring, 5-3
idle, powerdown, reset status, A-8, A-9 overview, 5-1
P2.7 reset status, 5-2 Port 3
idle, powerdown, reset status, A-8, A-9 internal structure, 5-5
overview, 5-1 Port 4
idle, powerdown, reset status, A-8, A-9 internal structure, 5-5
overview, 5-1 Port 5
configuring, 5-3
idle, powerdown, reset status, A-8, A-9 overview, 5-1
Port 6 configuring, 5-3
idle, powerdown, reset status, A-8, A-9 overview, 5-1
Ports, input buffers, 5-2
Powerdown mode, pin status, A-8, A-9 PTS select register, 4-7
PTS service register, 4-8
R
RD#, idle, powerdown, reset status, A-8, A-9 Register file
and windowing, 3-2 description, 3-3
Registers EPA_MASK, 7-4 EPA_MASK1, 7-4 EPA_PEND, 7-5 EPA_PEND1, 7-5 EPAIPV, 7-6 INT_MASK, 4-3
INT_MASK1, 4-4
INT_PEND, 4-5
INT_PEND1, 4-6 J_CFG, 8-18 J_CMD, 8-17 J_DLY, 8-20 J_RX, 8-15 J_STAT, 8-21 J_TX, 8-14 PTSSEL, 4-7 PTSSRV, 4-8 RSTSRC, 9-1 SSIO0_CLK, 6-1 SSIO1_CLK, 6-2 USFR1, 2-6
Reset
pin status, A-8,A-9
status of CLKOUT/P2.7, 5-2 Reset source indicator register, 9-1
RESET#, idle, powerdown, reset status, A-8,A-9
S
Serial port programming mode, 11-5 Signals
default conditions, A-8, A-9 status symbols defined, A-7
State time, defined, 2-4Symbols, signal status, A-7 Synchronous serial port 0 clock register, 6-1 Synchronous serial port 1 clock register, 6-2
U
Unerasable PROM 1 register, 2-6
W
Windows
and address-mapped SFRs, 3-6 locations that cannot be windowed, 3-6 WSR values and direct addresses, 3-6
WR#, idle, powerdown, reset status, A-8, A-9