Jcmd, Auto IFR Ignore Abort MSG3 MSG2 MSG1 MSG0 | Intel 87C196CA

J1850 COMMUNICATIONS CONTROLLER

J_CMD	Address:	1F51H
	Reset State:	00H

The J1850 command (J_CMD) register determines the messaging type, specifies the number of bytes to be transmitted in the next message frame, and updates the status of the message transmission in progress. This byte register can be directly addressed through windowing. You must write to this register prior to transmitting every message.

7

AUTO	IFR	IGNORE	ABORT

0

MSG3	MSG2	MSG1	MSG0

Bit	Bit				Function
Number	Mnemonic				Function
Number	Mnemonic

7	AUTO	Automatic Transmit Retry
		This bit, when arbitration is lost on the first byte of your message, prompts
		the transmitter to automatically retry until the byte is successfully
		transmitted. Automatic retry applies only to the first byte.
		0	= normal operation
		1	= enable automatic retry

6	IFR	In-frame Response Indicator
		This bit signals that a normalization bit (NB) is to be sent after an end-of-
		data symbol is detected on the bus and that the subsequent byte written to
		the J1850 transmitter (J_TX) register is an in-frame response (IFR).
		0	= standard messaging
		1	= next byte written to J_TX is an IFR

5	IGNORE	Ignore Incoming Message
		This bit instructs the bus to ignore the incoming message until an EOF
		symbol is detected. The bit is cleared after an EOF symbol is detected.
		0	= normal operation
		1	= ignore incoming message

4	ABORT	Abort Transmission
		This bit aborts any transmission in progress and flushes the transmit buffer
		(JTX_BUF). To prevent another node from mistakenly assuming that the
		last byte was a CRC byte, two extra ‘1’s are appended.
		0	= normal operation
		1	= abort transmission in progress

3:0	MSG3:0	Message
		These four bits specify the number of bytes to be transmitted in the next
		message frame. This number includes the header, but not the CRC byte. In
		normal messaging, the maximum number of bytes you can transmit in a
		message frame is eleven.
		MSG3:0		Operation	Purpose
		FH		Termination byte	Terminate block transmission
		EH		Block transmission	Transmit unspecified number of bytes
		DH		Reserved	—
		CH		Reserved	—
		B:0H		Normal messaging	Transmit specified number of bytes

Figure 8-16. J1850 Command (J_CMD) Register

8-17

Image 83

Intel 87C196CA, 8XC196Jx, 8XC196Lx, 8XC196Kx Jcmd, Auto IFR Ignore Abort MSG3 MSG2 MSG1 MSG0, MSG30 Operation Purpose

Contents

August Page Contents 8XC196LX Supplement Chapter Synchronous Serial I/O Port Internal Timing Entering and Exiting Once ModeFunctional Groupings of Signals Default Conditions Programming the J1850 Controller Figures 11-3 Tables Guide to This Manual Page Chapter Guide to this Manual Manual Contents Related Documents Related Documents Architectural Overview Page Chapter Architectural Overview Microcontroller FeaturesFeatures of the 8XC196Lx and 8XC196Kx Product Famiies Internal Timing Block Diagram Clock Circuitry 87C196LA, LB Only 16 MHz State Times at Various FrequenciesMHz 12 MHz Multiplier State Time External TimingPllen CLK1 CLK0 Internal PeripheralsUprom Programming Values and Locations 4 J1850 Communications Controller 1 I/O PortsSynchronous Serial I/O Port Event Processor ArrayPage Address Space Page Address Map Chapter Address SpaceAddress Partitions 1BFF Register File JR, KR AddressCA,JT,KT USFR1 LA, LB Peripheral SPECIAL-FUNCTION RegistersXC196Lx Peripheral SFRs Jdly SSIO1CLKSSIO0CLK Rstsrc Windows Windowing Upper Register File CA, JT, JV, KT, LA, LB BaseUpper Register File CA, JT, JV, KT 25H 0120H 49H 0100H 48H 24H 12H 4BH0140H Standard and PTS Interrupts Page Interrupt SOURCES, VECTORS, and Priorities Chapter Standard and PTS Interrupts Interrupt Source Mnemonic Priority Name Interrupt Controller PTS ServiceInterrupt Registers Interrupt Sources, Vectors, and Priorities Bit Mnemonic Interrupt Description Interrupt Mask RegistersIntmask Bit Function Number NMI Extint SSIO1 SSIO0 Interrupt Pending RegistersINTMASK1 LA, LD Intpend Interrupt Pending Intpend Register NMI Peripheral Transaction Server RegistersINTPEND1 Interrupt PTS Vector PtsselBit Interrupt Standard Vector PtssrvBits Ports Page EPA, Ssio Chapter PortsI/O Ports Overview Microcontroller Ports 8XC196LX Supplement Ports 1, 2, 5, and 6 Internal Structure 87C196LA, LB Only Configuring Ports 1, 2, 5, and 6 Bidirectional Ports Special Bidirectional Port Considerations For complementary output configurations Internal Structure for Ports 3 and 4 ADDRESS/DATA BUS 8XC196L X Supplement Synchronous Serial Port Page For receptions Chapter Synchronous Serial I/O PortSsio 0 Clock Register Bit Function CHS Ssio 1 Clock Register1FB7H CHS DUP Conint Conpnd Phas Pols SSIO1CLK Page Event Processor Array Page Device Capture/Compare Compare-only Chapter Event Processor ArrayEPA Functional Overview EPA Channels EPA Block Diagram 87C196LA, LB Only EPA Block Diagram 83C196LD Only EPAMASK1 EPA Mask RegistersEpamask EPAPEND1 EPA Pending RegistersEpapend Epaipv EPA Interrupt Priority Vector RegisterValue Interrupt J1850 Communications Controller Page PLL Clkout J1850 Communications ControllerJ1850 Functional Overview J1850 Communications Controller Block Diagram Control and Status Registers J1850 Controller Signals and RegistersJ1850 Controller Signals Signal Cyclic Redundancy Check Generator J1850 Controller OperationControl State Machine Bit Arbitration Symbol Synchronization and Timing CircuitryBus Contention Error Detection Digital Filter Delay CompensationSymbol Encoding and Decoding Clock Prescaler Bit Arbitration Example Huntzicker Symbol Definition for J1850 Bit Arbitration Example Message Frames Normalization Bit Standard MessagingHeader CRC Byte 64µS 128µS NB for IFR with CRC NB for IFR without CRC Name Symbol Bus Level TXmin TXnom TXmax RXmin RXmax Units Huntzicker Symbol Timing Characteristics IFR Messaging Type 1 Single Byte, Single Responder In-frame Response Messaging Transmitting Messages Transmitting and Receiving Messages CPU JTX Jtxbuf Transmit Byte CPU Jrxbuf Receiving MessagesReceive Byte Programming the J1850 Controller Programming the J1850 Command Jcmd RegisterIFR Messages MSG30 Operation Purpose JcmdAuto IFR Ignore Abort MSG3 MSG2 MSG1 MSG0 Auto IFR without CRC Byte Programming the J1850 Configuration Jcfg RegisterNBF IFR3 4XM Txbrk Rxpol PRE1 PRE0 NBF PRE1 PRE0 Programming the J1850 Delay Compensation Jdly Register 18. J1850 Delay Jdly Register Jstat Programming the J1850 Status Jstat Register Msgrx Msgtx Minimum Hardware Considerations Page Minimum Hardware Considerations Identifying the Reset Source Design Considerations for 8XC196LA, LB, and LD Special Operating Modes Page Chapter Special Operating Modes Entering and Exiting Once Mode 10-3 Page Programming Nonvolatile Memory Page Signature Word and Programming Voltage Values Programming the Nonvolatile MemorySignature Word and Programming Voltage Values Otprom Address MAP CCB1 Slave Programming Circuit and Address MAPC196LA, LB Otprom Address Map Address Range Description Hex Description Address Comments Serial Port Programming Circuit Serial Port Programming Circuit and Address MAP Do not address Serial Port Programming Mode Address MapDescription Address Range A000-FFFFHPage Signal Descriptions Page Functional Groupings of Signals Appendix a Signal Descriptions Table A-1 C196LA Signals Arranged by Functional Categories Signal Descriptions Table A-2 C196LB Signals Arranged by Functional Categories Figure A-2 C196LB 52-pin Plcc Package Bus Control & Status Table A-3 C196LD Signals Arranged by Functional CategoriesInput Name Pin Input/Output Cont’d Name Pin Default Conditions Signals Functions Table A-5 C196LA, LB Default Signal ConditionsPort Alternate During RESET# Upon RESET# Power Table A-6 C196LD Default Signal Conditions Page Glossary Page BIT GlossaryALU Byte ESD DOUBLE-WORDEPA Integer FET LSW ISRLONG-INTEGER LSB MSW MSB PIC PIH PLL Ptscb PSWPTS Ralu QUAD-WORD SHORT-INTEGER SARSFR Uart Word VPWWDT Index Page Clkout Index Index-2