SSIO1CLK, SSIO0CLK, Rstsrc, Jdly, Jcfg, Jstat JRX | Intel 8XC196Lx

ADDRESS SPACE

Table 3-3. 8XC196Lx Peripheral SFRs (Continued)

SIO and SSIO SFRs

Address	High (Odd) Byte	Low (Even) Byte
1FBEH	Reserved	Reserved
1FBCH	SP_BAUD (H)	SP_BAUD (L)
1FBAH	SP_CON	SBUF_TX
1FB8H	SP_STATUS	SBUF_RX
1FB6H	SSIO1_CLK	Reserved
1FB4H	SSIO0_CLK	SSIO_BAUD
1FB2H	SSIO1_CON	SSIO1_BUF
1FB0H	SSIO0_CON	SSIO0_BUF
	A/D SFRs (LA, LB Only)
Address	High (Odd) Byte	Low (Even) Byte
1FAEH	AD_TIME	AD_TEST
1FACH	Reserved	AD_COMMAND
1FAAH	AD_RESULT (H)	AD_RESULT (L)
	EPA Interrupt SFRs
Address	High (Odd) Byte	Low (Even) Byte
1FA8H	Reserved	EPAIPV
1FA6H	Reserved	EPA_PEND1
1FA4H	Reserved	EPA_MASK1
† 1FA2H	EPA_PEND (H)	EPA_PEND (L)
† 1FA0H	EPA_MASK (H)	EPA_MASK (L)
Timer 1, Timer 2, and EPA SFRs
Address	High (Odd) Byte	Low (Even) Byte
† 1F9EH	TIMER2 (H)	TIMER2 (L)
1F9CH	Reserved	T2CONTROL
† 1F9AH	TIMER1 (H)	TIMER1 (L)
1F98H	Reserved	T1CONTROL
1F96H	Reserved	Reserved
1F94H	Reserved	Reserved
1F92H	Reserved	RST_SRC
1F90H	Reserved	Reserved
	EPA SFRs
Address	High (Odd) Byte	Low (Even) Byte
† 1F8EH	COMP1_TIME (H)	COMP1_TIME (L)
1F8CH	Reserved	COMP1_CON
† 1F8AH	COMP0_TIME (H)	COMP0_TIME (L)
1F88H	Reserved	COMP0_CON
† 1F86H	EPA9_TIME (H)	EPA9_TIME (L)
1F84H	Reserved	EPA9_CON
† 1F82H	EPA8_TIME (H)	EPA8_TIME (L)
1F80H	Reserved	EPA8_CON

†Must be addressed as a word.

EPA SFRs (Continued)

Address	High (Odd) Byte	Low (Even) Byte
† 1F7EH	EPA7_TIME (H)	EPA7_TIME (L)
1F7CH	Reserved	EPA7_CON
† 1F7AH	EPA6_TIME (H)	EPA6_TIME (L)
1F78H	Reserved	EPA6_CON
† 1F76H	EPA5_TIME (H)	EPA5_TIME (L)
1F74H	Reserved	EPA5_CON
† 1F72H	EPA4_TIME (H)	EPA4_TIME (L)
1F70H	Reserved	EPA4_CON
† 1F6EH	EPA3_TIME (H)	EPA3_TIME (L)
† 1F6CH	EPA3_CON (H)	EPA3_CON (L)
† 1F6AH	EPA2_TIME (H)	EPA2_TIME (L)
1F68H	Reserved	EPA2_CON
† 1F66H	EPA1_TIME (H)	EPA1_TIME (L)
† 1F64H	EPA1_CON (H)	EPA1_CON (L)
† 1F62H	EPA0_TIME (H)	EPA0_TIME (L)
1F60H	Reserved	EPA0_CON
	J1850 SFRs (LB Only)
Address	High (Odd) Byte	Low (Even) Byte
1F5EH	Reserved	Reserved
1F5CH	Reserved	Reserved
1F5AH	Reserved	Reserved
1F58H	Reserved	J_DLY
1F56H	Reserved	Reserved
1F54H	Reserved	J_CFG
1F52H	J_STAT	J_RX
1F50H	J_CMD	J_TX

3-5

Image 29

Intel 8XC196Lx, 8XC196Jx, 8XC196Kx, 87C196CA user manual SSIO1CLK, SSIO0CLK, Rstsrc, Jdly, Jcfg, Jstat JRX, Jcmd JTX

Contents

August Page Contents 8XC196LX Supplement Chapter Synchronous Serial I/O Port Functional Groupings of Signals Default Conditions Entering and Exiting Once ModeProgramming the J1850 Controller Internal Timing Figures 11-3 Tables Guide to This Manual Page Chapter Guide to this Manual Manual Contents Related Documents Related Documents Architectural Overview Page Chapter Architectural Overview Microcontroller FeaturesFeatures of the 8XC196Lx and 8XC196Kx Product Famiies Internal Timing Block Diagram Clock Circuitry 87C196LA, LB Only MHz State Times at Various Frequencies12 MHz 16 MHz Multiplier State Time External TimingPllen CLK1 CLK0 Internal PeripheralsUprom Programming Values and Locations Synchronous Serial I/O Port 1 I/O PortsEvent Processor Array 4 J1850 Communications ControllerPage Address Space Page Address Map Chapter Address SpaceAddress Partitions 1BFF Register File JR, KR AddressCA,JT,KT USFR1 LA, LB Peripheral SPECIAL-FUNCTION RegistersXC196Lx Peripheral SFRs SSIO0CLK SSIO1CLKRstsrc Jdly Windows Windowing Upper Register File CA, JT, JV, KT, LA, LB BaseUpper Register File CA, JT, JV, KT 25H 0120H 49H 0100H 48H 24H 12H 4BH0140H Standard and PTS Interrupts Page Interrupt SOURCES, VECTORS, and Priorities Chapter Standard and PTS Interrupts Interrupt Registers Interrupt Controller PTS ServiceInterrupt Sources, Vectors, and Priorities Interrupt Source Mnemonic Priority Name Intmask Interrupt Mask RegistersBit Function Number Bit Mnemonic Interrupt Description INTMASK1 Interrupt Pending RegistersLA, LD NMI Extint SSIO1 SSIO0 Intpend Interrupt Pending Intpend Register NMI Peripheral Transaction Server RegistersINTPEND1 Interrupt PTS Vector PtsselBit Interrupt Standard Vector PtssrvBits Ports Page I/O Ports Overview Chapter PortsMicrocontroller Ports EPA, Ssio 8XC196LX Supplement Ports 1, 2, 5, and 6 Internal Structure 87C196LA, LB Only Configuring Ports 1, 2, 5, and 6 Bidirectional Ports Special Bidirectional Port Considerations For complementary output configurations Internal Structure for Ports 3 and 4 ADDRESS/DATA BUS 8XC196L X Supplement Synchronous Serial Port Page Ssio 0 Clock Register Chapter Synchronous Serial I/O PortBit Function For receptions 1FB7H Ssio 1 Clock RegisterCHS DUP Conint Conpnd Phas Pols CHS SSIO1CLK Page Event Processor Array Page EPA Functional Overview Chapter Event Processor ArrayEPA Channels Device Capture/Compare Compare-only EPA Block Diagram 87C196LA, LB Only EPA Block Diagram 83C196LD Only EPAMASK1 EPA Mask RegistersEpamask EPAPEND1 EPA Pending RegistersEpapend Epaipv EPA Interrupt Priority Vector RegisterValue Interrupt J1850 Communications Controller Page PLL Clkout J1850 Communications ControllerJ1850 Functional Overview J1850 Communications Controller Block Diagram J1850 Controller Signals J1850 Controller Signals and RegistersSignal Control and Status Registers Cyclic Redundancy Check Generator J1850 Controller OperationControl State Machine Bus Contention Symbol Synchronization and Timing CircuitryError Detection Bit Arbitration Symbol Encoding and Decoding Delay CompensationClock Prescaler Digital Filter Bit Arbitration Example Huntzicker Symbol Definition for J1850 Bit Arbitration Example Message Frames Header Standard MessagingCRC Byte Normalization Bit 64µS 128µS NB for IFR with CRC NB for IFR without CRC Name Symbol Bus Level TXmin TXnom TXmax RXmin RXmax Units Huntzicker Symbol Timing Characteristics IFR Messaging Type 1 Single Byte, Single Responder In-frame Response Messaging Transmitting Messages Transmitting and Receiving Messages CPU JTX Jtxbuf Transmit Byte CPU Jrxbuf Receiving MessagesReceive Byte Programming the J1850 Controller Programming the J1850 Command Jcmd RegisterIFR Messages Auto IFR Ignore Abort MSG3 MSG2 MSG1 MSG0 JcmdAuto MSG30 Operation Purpose NBF IFR3 4XM Txbrk Rxpol PRE1 PRE0 Programming the J1850 Configuration Jcfg RegisterNBF IFR without CRC Byte PRE1 PRE0 Programming the J1850 Delay Compensation Jdly Register 18. J1850 Delay Jdly Register Jstat Programming the J1850 Status Jstat Register Msgrx Msgtx Minimum Hardware Considerations Page Minimum Hardware Considerations Identifying the Reset Source Design Considerations for 8XC196LA, LB, and LD Special Operating Modes Page Chapter Special Operating Modes Entering and Exiting Once Mode 10-3 Page Programming Nonvolatile Memory Page Signature Word and Programming Voltage Values Programming the Nonvolatile MemoryOtprom Address MAP Signature Word and Programming Voltage Values C196LA, LB Otprom Address Map Slave Programming Circuit and Address MAPAddress Range Description Hex CCB1 Description Address Comments Serial Port Programming Circuit Serial Port Programming Circuit and Address MAP Description Address Range Serial Port Programming Mode Address MapA000-FFFFH Do not addressPage Signal Descriptions Page Functional Groupings of Signals Appendix a Signal Descriptions Table A-1 C196LA Signals Arranged by Functional Categories Signal Descriptions Table A-2 C196LB Signals Arranged by Functional Categories Figure A-2 C196LB 52-pin Plcc Package Input Name Pin Table A-3 C196LD Signals Arranged by Functional CategoriesInput/Output Cont’d Name Pin Bus Control & Status Default Conditions Signals Functions Table A-5 C196LA, LB Default Signal ConditionsPort Alternate During RESET# Upon RESET# Power Table A-6 C196LD Default Signal Conditions Page Glossary Page BIT GlossaryALU Byte ESD DOUBLE-WORDEPA Integer FET LONG-INTEGER ISRLSB LSW MSW MSB PIC PIH PLL Ptscb PSWPTS Ralu QUAD-WORD SHORT-INTEGER SARSFR Uart Word VPWWDT Index Page Clkout Index Index-2