nonlinearity

nonmaskable interrupts

npn transistor

off-isolation

p-channel FET

p-type material

PC phase-locked loop

PIC

PIH

PLL

GLOSSARY

The maximum deviation of code transitions of the terminal-based characteristic from the corre- sponding code transitions of the ideal characteristic.

Interrupts that cannot be masked (disabled) and cannot be assigned to the PTS for processing. The nonmaskable interrupts are stack overflow, unimple- mented opcode, software trap, and NMI. The DI (disable interrupt service) and EI (enable interrupt service) instructions have no effect on nonmaskable interrupts.

A transistor consisting of one part p-type material and two parts n-type material.

The ability of an A/D converter to reject (isolate) the signal on a deselected (off) output.

Afield-effect transistor with a p-type conducting path.

Semiconductor material with introduced impurities (doping) causing it to have an excess of positively charged carriers.

Program counter.

A component of the clock generation circuitry. The phase-locked loop (PLL) and the input pin (PLLEN) combine to enable the microcontroller to attain its maximum operating frequency with an external clock whose frequency is either equal to or one-half that maximum frequency or with an external oscillator whose frequency is one-half that maximum frequency.

Programmable interrupt controller. The module responsible for handling interrupts that are to be serviced by interrupt service routines that you provide. Also called simply the interrupt controller.

Peripheral interrupt handler. An integrated module that provides interrupt vectors for specific EPA interrupt requests to the interrupt controller or PTS.

See phase-locked loop.

Glossary-7

Page 127
Image 127
Intel 87C196CA, 8XC196Jx, 8XC196Lx, 8XC196Kx user manual Pic Pih Pll