CHAPTER 8 J1850 COMMUNICATIONS CONTROLLER

The J1850 communications controller manages communications between multiple network nodes. This integrated peripheral supports the 10.4 Kb/s VPW (variable pulse width) medium- speed class B in-vehicle network protocol. It also supports both the standard and in-frame re- sponse (IFR) message framing as specified by the Society of Automotive Engineering (SAE) J1850 (revised May 1994) technical standards. Its lower cost per node makes it suitable for diag- nostics and non-real-time data sharing in applications with high numbers of nodes. This chapter details the integrated J1850 controller and explains how to configure it.

8.1J1850 FUNCTIONAL OVERVIEW

The integrated J1850 communications controller transfers messages between network nodes ac- cording to the J1850 protocol. The complete J1850 communications protocol solution includes an on-chip, J1850 digital-logic controller working with an external analog bus transceiver circuit. Figure 8-1 illustrates the J1850 protocol with the J1850 controller integrated on the 87C196LB 16-bit microcontroller and a standalone J1850 bus transceiver device. The example uses the Har- ris HIP7020 as the remote transceiver device.

 

TXJ1850

TX

J1850

 

 

HIP7020

Bus

 

RXJ1850

RX

 

 

87C196LB

 

 

 

Microcontroller

 

 

Clock

PLL/

 

 

CLKOUT

 

 

 

 

 

 

 

 

A5168-01

Figure 8-1. Integrated J1850 Communications Protocol Solution

The benefit of an integrated, J1850 protocol solution is threefold:

Minimizes CPU overhead for reception and transmission of J1850 messages.

Frees up serial and parallel communications ports for other purposes.

Offers significant printed-circuit board area savings when compared with conventional standalone protocol devices.

8-1

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Intel 87C196CA, 8XC196Jx, 8XC196Lx, 8XC196Kx J1850 Communications Controller, J1850 Functional Overview, PLL Clkout