J1850 Communications Controller Block Diagram | Intel 8XC196Jx

8XC196LX SUPPLEMENT

The J1850 controller can handle network protocol functions including message frame sequenc- ing, bit arbitration, in-frame response (IFR) messaging, error detection, and delay compensation.

The J1850 communications controller (Figure 8-2) consists of a control state machine (CSM), symbol synchronization and timing (SST) circuitry, six control and status registers, transmit and receive buffers, and an interrupt handler.

J1850ST		Bus Error	J1850 Communications Controller
J1850ST		Bus Error
J1850RX	Interrupt	RX
J1850TX	Handler	TX
J1850TX		TX
	J_DLY
	J_STAT
OVR		Error
OVR		Detection
UNDR		Detection
UNDR		Circuitry
Bus	J_TX
Bus				Delay
Data			Symbol	Compensator	TXJ1850
			Symbol
	JTX_BUF	Bit	Encoder
Peripheral		Bit	Encoder
		Arbitration
		Arbitration	Symbol
	JRX_BUF	Circuitry	Symbol	Digital
	JRX_BUF	Circuitry	Decoder	Digital
			Decoder	Filter
		Cyclic		Filter	RXJ1850


		Redundancy
	J_RX	Check Circuitry	Prescaler
	J_CMD	CSM		SST
	J_CMD
	J_CFG
Internal Clocking
					A5169-01

Figure 8-2. J1850 Communications Controller Block Diagram

8-2

Image 68

Intel 8XC196Jx, 8XC196Lx, 8XC196Kx, 87C196CA user manual J1850 Communications Controller Block Diagram

Contents

August Page Contents 8XC196LX Supplement Chapter Synchronous Serial I/O Port Entering and Exiting Once Mode Functional Groupings of Signals Default ConditionsProgramming the J1850 Controller Internal Timing Figures 11-3 Tables Guide to This Manual Page Manual Contents Chapter Guide to this Manual Related Documents Related Documents Architectural Overview Page Chapter Architectural Overview Microcontroller FeaturesFeatures of the 8XC196Lx and 8XC196Kx Product Famiies Block Diagram Internal Timing Clock Circuitry 87C196LA, LB Only State Times at Various Frequencies MHz12 MHz 16 MHz Multiplier State Time External TimingPllen CLK1 CLK0 Internal PeripheralsUprom Programming Values and Locations 1 I/O Ports Synchronous Serial I/O PortEvent Processor Array 4 J1850 Communications ControllerPage Address Space Page Address Map Chapter Address SpaceAddress Partitions Register File 1BFF JR, KR AddressCA,JT,KT USFR1 LA, LB Peripheral SPECIAL-FUNCTION RegistersXC196Lx Peripheral SFRs SSIO1CLK SSIO0CLKRstsrc Jdly Windowing Windows Upper Register File CA, JT, JV, KT, LA, LB BaseUpper Register File CA, JT, JV, KT 25H 0120H 49H 0100H 48H 24H 12H 4BH0140H Standard and PTS Interrupts Page Chapter Standard and PTS Interrupts Interrupt SOURCES, VECTORS, and Priorities Interrupt Controller PTS Service Interrupt RegistersInterrupt Sources, Vectors, and Priorities Interrupt Source Mnemonic Priority Name Interrupt Mask Registers IntmaskBit Function Number Bit Mnemonic Interrupt Description Interrupt Pending Registers INTMASK1LA, LD NMI Extint SSIO1 SSIO0 Interrupt Pending Intpend Register Intpend NMI Peripheral Transaction Server RegistersINTPEND1 Interrupt PTS Vector PtsselBit Interrupt Standard Vector PtssrvBits Ports Page Chapter Ports I/O Ports OverviewMicrocontroller Ports EPA, Ssio 8XC196LX Supplement Configuring Ports 1, 2, 5, and 6 Bidirectional Ports Ports 1, 2, 5, and 6 Internal Structure 87C196LA, LB Only For complementary output configurations Special Bidirectional Port Considerations Internal Structure for Ports 3 and 4 ADDRESS/DATA BUS 8XC196L X Supplement Synchronous Serial Port Page Chapter Synchronous Serial I/O Port Ssio 0 Clock RegisterBit Function For receptions Ssio 1 Clock Register 1FB7HCHS DUP Conint Conpnd Phas Pols CHS SSIO1CLK Page Event Processor Array Page Chapter Event Processor Array EPA Functional OverviewEPA Channels Device Capture/Compare Compare-only EPA Block Diagram 87C196LA, LB Only EPA Block Diagram 83C196LD Only EPAMASK1 EPA Mask RegistersEpamask EPAPEND1 EPA Pending RegistersEpapend Epaipv EPA Interrupt Priority Vector RegisterValue Interrupt J1850 Communications Controller Page PLL Clkout J1850 Communications ControllerJ1850 Functional Overview J1850 Communications Controller Block Diagram J1850 Controller Signals and Registers J1850 Controller SignalsSignal Control and Status Registers Cyclic Redundancy Check Generator J1850 Controller OperationControl State Machine Symbol Synchronization and Timing Circuitry Bus ContentionError Detection Bit Arbitration Delay Compensation Symbol Encoding and DecodingClock Prescaler Digital Filter Huntzicker Symbol Definition for J1850 Bit Arbitration Example Message Frames Bit Arbitration Example Standard Messaging HeaderCRC Byte Normalization Bit 64µS 128µS NB for IFR with CRC NB for IFR without CRC Huntzicker Symbol Timing Characteristics Name Symbol Bus Level TXmin TXnom TXmax RXmin RXmax Units In-frame Response Messaging IFR Messaging Type 1 Single Byte, Single Responder Transmitting and Receiving Messages Transmitting Messages Transmit Byte CPU JTX Jtxbuf CPU Jrxbuf Receiving MessagesReceive Byte Programming the J1850 Controller Programming the J1850 Command Jcmd RegisterIFR Messages Jcmd Auto IFR Ignore Abort MSG3 MSG2 MSG1 MSG0Auto MSG30 Operation Purpose Programming the J1850 Configuration Jcfg Register NBF IFR3 4XM Txbrk Rxpol PRE1 PRE0NBF IFR without CRC Byte Programming the J1850 Delay Compensation Jdly Register PRE1 PRE0 18. J1850 Delay Jdly Register Programming the J1850 Status Jstat Register Jstat Msgtx Msgrx Minimum Hardware Considerations Page Identifying the Reset Source Minimum Hardware Considerations Design Considerations for 8XC196LA, LB, and LD Special Operating Modes Page Chapter Special Operating Modes Entering and Exiting Once Mode 10-3 Page Programming Nonvolatile Memory Page Programming the Nonvolatile Memory Signature Word and Programming Voltage ValuesOtprom Address MAP Signature Word and Programming Voltage Values Slave Programming Circuit and Address MAP C196LA, LB Otprom Address MapAddress Range Description Hex CCB1 Description Address Comments Serial Port Programming Circuit and Address MAP Serial Port Programming Circuit Serial Port Programming Mode Address Map Description Address RangeA000-FFFFH Do not addressPage Signal Descriptions Page Appendix a Signal Descriptions Functional Groupings of Signals Table A-1 C196LA Signals Arranged by Functional Categories Signal Descriptions Table A-2 C196LB Signals Arranged by Functional Categories Figure A-2 C196LB 52-pin Plcc Package Table A-3 C196LD Signals Arranged by Functional Categories Input Name PinInput/Output Cont’d Name Pin Bus Control & Status Default Conditions Signals Functions Table A-5 C196LA, LB Default Signal ConditionsPort Alternate During RESET# Upon RESET# Power Table A-6 C196LD Default Signal Conditions Page Glossary Page BIT GlossaryALU Byte ESD DOUBLE-WORDEPA FET Integer ISR LONG-INTEGERLSB LSW MSB MSW PIC PIH PLL Ptscb PSWPTS QUAD-WORD Ralu SHORT-INTEGER SARSFR Uart Word VPWWDT Index Page Index Clkout Index-2