Huntzicker Symbol Timing Characteristics | Intel 8XC196Lx, 8XC196Jx

J1850 COMMUNICATIONS CONTROLLER

200µS

1

0

"Start of Frame (SOF)"

1

200µS

0 "End of Data (EOD)"

1

280µS

0

"End of Frame (EOF)"

1

300µS+

0 "In-frame Separation (IFS)"

1			768µS+
			"Break Signal (BRK)"
0

A5221-01

Figure 8-8. Definition for Start and End of Frame Symbols

Table 8-4 details the symbol timing characteristics supported by the 87C196LB.

Table 8-4. Huntzicker Symbol Timing Characteristics

	Name	Symbol	Bus Level	TTXmin	TTXnom	TTXmax	TRXmin	TRXmax	Units

	Logic Level 0	0	Passive	60	64	68	34	<96	µs

			Active	122	128	134	96	<163	µs
			Active	122	128	134	96	<163	µs

	Logic Level 1	1	Passive	122	128	134	96	<163	µs

			Active	60	64	68	34	<96	µs
			Active	60	64	68	34	<96	µs

	Start of Frame	SOF	Active	193	200	207	163	<239	µs

	End of Data	EOD	Passive	193	200	207	163	<239	µs

	End of Frame	EOF	Passive	271	280	289	239	<300	µs

	In-frame Separation	IFS	Passive	>300	—	—	>300	—	µs

	Break	BRK	Active	768	—	—	>239	—	µs

NOTE: Timings are based on the standard bus rate of 10.4 Kb/s. When operating in 4x mode, the bus rate becomes 41.6 Kb/s and all symbol timings are one fourth that shown.

8-11

Image 77

Intel 8XC196Lx Huntzicker Symbol Timing Characteristics, Name Symbol Bus Level TXmin TXnom TXmax RXmin RXmax Units

Contents

August Page Contents 8XC196LX Supplement Chapter Synchronous Serial I/O Port Functional Groupings of Signals Default Conditions Entering and Exiting Once ModeProgramming the J1850 Controller Internal Timing Figures 11-3 Tables Guide to This Manual Page Chapter Guide to this Manual Manual Contents Related Documents Related Documents Architectural Overview Page Chapter Architectural Overview Microcontroller FeaturesFeatures of the 8XC196Lx and 8XC196Kx Product Famiies Internal Timing Block Diagram Clock Circuitry 87C196LA, LB Only MHz State Times at Various Frequencies12 MHz 16 MHz Multiplier State Time External TimingPllen CLK1 CLK0 Internal PeripheralsUprom Programming Values and Locations Synchronous Serial I/O Port 1 I/O PortsEvent Processor Array 4 J1850 Communications ControllerPage Address Space Page Address Map Chapter Address SpaceAddress Partitions 1BFF Register File JR, KR AddressCA,JT,KT USFR1 LA, LB Peripheral SPECIAL-FUNCTION RegistersXC196Lx Peripheral SFRs SSIO0CLK SSIO1CLKRstsrc Jdly Windows Windowing Upper Register File CA, JT, JV, KT, LA, LB BaseUpper Register File CA, JT, JV, KT 25H 0120H 49H 0100H 48H 24H 12H 4BH0140H Standard and PTS Interrupts Page Interrupt SOURCES, VECTORS, and Priorities Chapter Standard and PTS Interrupts Interrupt Registers Interrupt Controller PTS ServiceInterrupt Sources, Vectors, and Priorities Interrupt Source Mnemonic Priority Name Intmask Interrupt Mask RegistersBit Function Number Bit Mnemonic Interrupt Description INTMASK1 Interrupt Pending RegistersLA, LD NMI Extint SSIO1 SSIO0 Intpend Interrupt Pending Intpend Register NMI Peripheral Transaction Server RegistersINTPEND1 Interrupt PTS Vector PtsselBit Interrupt Standard Vector PtssrvBits Ports Page I/O Ports Overview Chapter PortsMicrocontroller Ports EPA, Ssio 8XC196LX Supplement Ports 1, 2, 5, and 6 Internal Structure 87C196LA, LB Only Configuring Ports 1, 2, 5, and 6 Bidirectional Ports Special Bidirectional Port Considerations For complementary output configurations Internal Structure for Ports 3 and 4 ADDRESS/DATA BUS 8XC196L X Supplement Synchronous Serial Port Page Ssio 0 Clock Register Chapter Synchronous Serial I/O PortBit Function For receptions 1FB7H Ssio 1 Clock RegisterCHS DUP Conint Conpnd Phas Pols CHS SSIO1CLK Page Event Processor Array Page EPA Functional Overview Chapter Event Processor ArrayEPA Channels Device Capture/Compare Compare-only EPA Block Diagram 87C196LA, LB Only EPA Block Diagram 83C196LD Only EPAMASK1 EPA Mask RegistersEpamask EPAPEND1 EPA Pending RegistersEpapend Epaipv EPA Interrupt Priority Vector RegisterValue Interrupt J1850 Communications Controller Page PLL Clkout J1850 Communications ControllerJ1850 Functional Overview J1850 Communications Controller Block Diagram J1850 Controller Signals J1850 Controller Signals and RegistersSignal Control and Status Registers Cyclic Redundancy Check Generator J1850 Controller OperationControl State Machine Bus Contention Symbol Synchronization and Timing CircuitryError Detection Bit Arbitration Symbol Encoding and Decoding Delay CompensationClock Prescaler Digital Filter Bit Arbitration Example Huntzicker Symbol Definition for J1850 Bit Arbitration Example Message Frames Header Standard MessagingCRC Byte Normalization Bit 64µS 128µS NB for IFR with CRC NB for IFR without CRC Name Symbol Bus Level TXmin TXnom TXmax RXmin RXmax Units Huntzicker Symbol Timing Characteristics IFR Messaging Type 1 Single Byte, Single Responder In-frame Response Messaging Transmitting Messages Transmitting and Receiving Messages CPU JTX Jtxbuf Transmit Byte CPU Jrxbuf Receiving MessagesReceive Byte Programming the J1850 Controller Programming the J1850 Command Jcmd RegisterIFR Messages Auto IFR Ignore Abort MSG3 MSG2 MSG1 MSG0 JcmdAuto MSG30 Operation Purpose NBF IFR3 4XM Txbrk Rxpol PRE1 PRE0 Programming the J1850 Configuration Jcfg RegisterNBF IFR without CRC Byte PRE1 PRE0 Programming the J1850 Delay Compensation Jdly Register 18. J1850 Delay Jdly Register Jstat Programming the J1850 Status Jstat Register Msgrx Msgtx Minimum Hardware Considerations Page Minimum Hardware Considerations Identifying the Reset Source Design Considerations for 8XC196LA, LB, and LD Special Operating Modes Page Chapter Special Operating Modes Entering and Exiting Once Mode 10-3 Page Programming Nonvolatile Memory Page Signature Word and Programming Voltage Values Programming the Nonvolatile MemoryOtprom Address MAP Signature Word and Programming Voltage Values C196LA, LB Otprom Address Map Slave Programming Circuit and Address MAPAddress Range Description Hex CCB1 Description Address Comments Serial Port Programming Circuit Serial Port Programming Circuit and Address MAP Description Address Range Serial Port Programming Mode Address MapA000-FFFFH Do not addressPage Signal Descriptions Page Functional Groupings of Signals Appendix a Signal Descriptions Table A-1 C196LA Signals Arranged by Functional Categories Signal Descriptions Table A-2 C196LB Signals Arranged by Functional Categories Figure A-2 C196LB 52-pin Plcc Package Input Name Pin Table A-3 C196LD Signals Arranged by Functional CategoriesInput/Output Cont’d Name Pin Bus Control & Status Default Conditions Signals Functions Table A-5 C196LA, LB Default Signal ConditionsPort Alternate During RESET# Upon RESET# Power Table A-6 C196LD Default Signal Conditions Page Glossary Page BIT GlossaryALU Byte ESD DOUBLE-WORDEPA Integer FET LONG-INTEGER ISRLSB LSW MSW MSB PIC PIH PLL Ptscb PSWPTS Ralu QUAD-WORD SHORT-INTEGER SARSFR Uart Word VPWWDT Index Page Clkout Index Index-2