IFR Messages, Programming the J1850 Controller | Intel 8XC196Kx

8XC196LX SUPPLEMENT

If a third byte is received before J_RX is read, a J1850ST core interrupt is generated and the OVR_UNDR (J_STAT.3) bit records a receiver overrun error in the J_STAT register.

8.5.3IFR Messages

In-frame response (IFR) messaging is identical in setup to standard messaging for both transmis- sion and reception. It uses the same registers to configure, communicate, and control data. The difference is that the requestor initiating the IFR message sequence writes the message specifying a response from either one or more nodes in the system. Framing a message in this manner by- passes needless CPU overhead that can result from lengthy EOF symbols, and it gives you a faster response to the information you are accessing from remote sites in your system. (Refer to “In- frame Response Messaging” on page 8-12 for a detailed explanation).

8.6PROGRAMMING THE J1850 CONTROLLER

This section explains how to configure the J1850 controller. Several registers combine to control the configuration: the command register, the configuration register, the delay compensation reg- ister, and the status register.

Programming the J1850 controller requires that you first program the configuration and delay registers during initialization. You need to program these two registers only once per initializa- tion sequence.

After initialization, you must first program the command register, followed by either the receive or transmit register, and then the status register.

8.6.1Programming the J1850 Command (J_CMD) Register

The J1850 command register (Figure 8-16) determines the messaging type, specifies the number of bytes to be transmitted in the next message frame, and updates the status of the message trans- mission in progress.

8-16

Image 82

Intel 8XC196Kx, 8XC196Jx IFR Messages, Programming the J1850 Controller, Programming the J1850 Command Jcmd Register

Contents

August Page Contents 8XC196LX Supplement Chapter Synchronous Serial I/O Port Programming the J1850 Controller Entering and Exiting Once ModeFunctional Groupings of Signals Default Conditions Internal Timing Figures 11-3 Tables Guide to This Manual Page Manual Contents Chapter Guide to this Manual Related Documents Related Documents Architectural Overview Page Features of the 8XC196Lx and 8XC196Kx Product Famiies Microcontroller FeaturesChapter Architectural Overview Block Diagram Internal Timing Clock Circuitry 87C196LA, LB Only 12 MHz State Times at Various FrequenciesMHz 16 MHz Pllen External TimingMultiplier State Time Uprom Programming Values and Locations Internal PeripheralsCLK1 CLK0 Event Processor Array 1 I/O PortsSynchronous Serial I/O Port 4 J1850 Communications ControllerPage Address Space Page Address Partitions Chapter Address SpaceAddress Map Register File 1BFF CA,JT,KT AddressJR, KR XC196Lx Peripheral SFRs Peripheral SPECIAL-FUNCTION RegistersUSFR1 LA, LB Rstsrc SSIO1CLKSSIO0CLK Jdly Windowing Windows Upper Register File CA, JT, JV, KT BaseUpper Register File CA, JT, JV, KT, LA, LB 0140H 4BH25H 0120H 49H 0100H 48H 24H 12H Standard and PTS Interrupts Page Chapter Standard and PTS Interrupts Interrupt SOURCES, VECTORS, and Priorities Interrupt Sources, Vectors, and Priorities Interrupt Controller PTS ServiceInterrupt Registers Interrupt Source Mnemonic Priority Name Bit Function Number Interrupt Mask RegistersIntmask Bit Mnemonic Interrupt Description LA, LD Interrupt Pending RegistersINTMASK1 NMI Extint SSIO1 SSIO0 Interrupt Pending Intpend Register Intpend INTPEND1 Peripheral Transaction Server RegistersNMI Bit PtsselInterrupt PTS Vector Bits PtssrvInterrupt Standard Vector Ports Page Microcontroller Ports Chapter PortsI/O Ports Overview EPA, Ssio 8XC196LX Supplement Configuring Ports 1, 2, 5, and 6 Bidirectional Ports Ports 1, 2, 5, and 6 Internal Structure 87C196LA, LB Only For complementary output configurations Special Bidirectional Port Considerations Internal Structure for Ports 3 and 4 ADDRESS/DATA BUS 8XC196L X Supplement Synchronous Serial Port Page Bit Function Chapter Synchronous Serial I/O PortSsio 0 Clock Register For receptions CHS DUP Conint Conpnd Phas Pols Ssio 1 Clock Register1FB7H CHS SSIO1CLK Page Event Processor Array Page EPA Channels Chapter Event Processor ArrayEPA Functional Overview Device Capture/Compare Compare-only EPA Block Diagram 87C196LA, LB Only EPA Block Diagram 83C196LD Only Epamask EPA Mask RegistersEPAMASK1 Epapend EPA Pending RegistersEPAPEND1 Value Interrupt EPA Interrupt Priority Vector RegisterEpaipv J1850 Communications Controller Page J1850 Functional Overview J1850 Communications ControllerPLL Clkout J1850 Communications Controller Block Diagram Signal J1850 Controller Signals and RegistersJ1850 Controller Signals Control and Status Registers Control State Machine J1850 Controller OperationCyclic Redundancy Check Generator Error Detection Symbol Synchronization and Timing CircuitryBus Contention Bit Arbitration Clock Prescaler Delay CompensationSymbol Encoding and Decoding Digital Filter Huntzicker Symbol Definition for J1850 Bit Arbitration Example Message Frames Bit Arbitration Example CRC Byte Standard MessagingHeader Normalization Bit 64µS 128µS NB for IFR with CRC NB for IFR without CRC Huntzicker Symbol Timing Characteristics Name Symbol Bus Level TXmin TXnom TXmax RXmin RXmax Units In-frame Response Messaging IFR Messaging Type 1 Single Byte, Single Responder Transmitting and Receiving Messages Transmitting Messages Transmit Byte CPU JTX Jtxbuf Receive Byte Receiving MessagesCPU Jrxbuf IFR Messages Programming the J1850 Command Jcmd RegisterProgramming the J1850 Controller Auto JcmdAuto IFR Ignore Abort MSG3 MSG2 MSG1 MSG0 MSG30 Operation Purpose NBF Programming the J1850 Configuration Jcfg RegisterNBF IFR3 4XM Txbrk Rxpol PRE1 PRE0 IFR without CRC Byte Programming the J1850 Delay Compensation Jdly Register PRE1 PRE0 18. J1850 Delay Jdly Register Programming the J1850 Status Jstat Register Jstat Msgtx Msgrx Minimum Hardware Considerations Page Identifying the Reset Source Minimum Hardware Considerations Design Considerations for 8XC196LA, LB, and LD Special Operating Modes Page Chapter Special Operating Modes Entering and Exiting Once Mode 10-3 Page Programming Nonvolatile Memory Page Otprom Address MAP Programming the Nonvolatile MemorySignature Word and Programming Voltage Values Signature Word and Programming Voltage Values Address Range Description Hex Slave Programming Circuit and Address MAPC196LA, LB Otprom Address Map CCB1 Description Address Comments Serial Port Programming Circuit and Address MAP Serial Port Programming Circuit A000-FFFFH Serial Port Programming Mode Address MapDescription Address Range Do not addressPage Signal Descriptions Page Appendix a Signal Descriptions Functional Groupings of Signals Table A-1 C196LA Signals Arranged by Functional Categories Signal Descriptions Table A-2 C196LB Signals Arranged by Functional Categories Figure A-2 C196LB 52-pin Plcc Package Input/Output Cont’d Name Pin Table A-3 C196LD Signals Arranged by Functional CategoriesInput Name Pin Bus Control & Status Default Conditions Port Alternate During RESET# Upon RESET# Power Table A-5 C196LA, LB Default Signal ConditionsSignals Functions Table A-6 C196LD Default Signal Conditions Page Glossary Page ALU GlossaryBIT Byte EPA DOUBLE-WORDESD FET Integer LSB ISRLONG-INTEGER LSW MSB MSW PIC PIH PLL PTS PSWPtscb QUAD-WORD Ralu SFR SARSHORT-INTEGER Uart WDT VPWWord Index Page Index Clkout Index-2