Table A-5 C196LA, LB Default Signal Conditions | Intel 8XC196Jx

8XC196LX SUPPLEMENT

Table A-5. 87C196LA, LB Default Signal Conditions

	Port	Alternate	During RESET#	Upon RESET#		Power-
	Port	Alternate	During RESET#	Inactive	Idle	Power-
	Signals	Functions	Active	Inactive	Idle	down
	Signals	Functions	Active	(Note 6)		down
				(Note 6)

	P0.7:2	ACH7:2	HiZ	HiZ	HiZ	HiZ
	P1.0	EPA0/T2CLK	WK0	WK0	(Note 1)	(Note 1)
	P1.1	EPA1	WK0	WK0	(Note 1)	(Note 1)
	P1.2	EPA2/T2DIR	WK0	WK0	(Note 1)	(Note 1)
	P1.3	EPA3	WK0	WK0	(Note 1)	(Note 1)
	P2.0	TXD	WK0	WK0	(Note 1)	(Note 1)
	P2.1	RXD	WK0	WK0	(Note 1)	(Note 1)
	P2.2	EXTINT	WK0	WK0	(Note 1)	(Note 1)
	P2.4	RXJ1850 (LB only)	WK0	WK0	(Note 1)	(Note 1)
	P2.6	ONCE/TXJ1850 (LB only)	MD0	MD0	(Note 1)	(Note 1)
	P2.7	CLKOUT	CLKOUT active,	CLKOUT active,	(Note 1)	(Note 2)
			LoZ0/1	LoZ0/1
	P3.7:0	AD7:0	WK0	HiZ	(Note 4)	(Note 4)
	P4.7:0	AD15:8	WK0	HiZ	(Note 4)	(Note 4)
	P5.0	ALE/ADV#	WK0	WK0	(Note 1)	(Note 1)
	P5.2	WR#/WRL#	WK0	WK0	(Note 1)	(Note 1)
	P5.3	RD#	WK0	WK0	(Note 1)	(Note 1)
	P6.0	EPA8/COMP0	WK0	WK0	(Note 1)	(Note 1)
	P6.1	EPA9/COMP1	WK0	WK0	(Note 1)	(Note 1)
	P6.4	SC0	WK0	WK0	(Note 1)	(Note 1)
	P6.5	SD0	WK0	WK0	(Note 1)	(Note 1)
	P6.6	SC1	WK0	WK0	(Note 1)	(Note 1)
	P6.7	SD1	WK0	WK0	(Note 1)	(Note 1)
	—	EA#	WK1 (Note 5)	WK1	WK1	WK1
	—	RESET#	LoZ0	MD1	MD1	MD1
	—	V PP	HiZ	HiZ	LoZ1	LoZ1
	—	XTAL1	Osc input, HiZ	Osc input, HiZ	Osc input,	Osc input,
			Osc input, HiZ	Osc input, HiZ	HiZ	HiZ
					HiZ	HiZ
	—	XTAL2	Osc output,	Osc output,	Osc output,	(Note 3)
			LoZ0/1	LoZ0/1	LoZ0/1

NOTES:

1.If Px_MODE.y = 0, port is as programmed.

If Px_MODE.y = 1, pin is as specified by Px_DIR and the associated peripheral.

2.If P2_MODE.7 = 0, pin is as programmed. If P2_MODE.7 = 1, pin is LoZ0.

3.If XTAL1 = 0, pin is LoZ1. If XTAL1 = 1, pin is LoZ0.

4.If EA# = 0, port is HiZ. If EA# = 1, port is open-drain I/O.

5.Although EA# is weakly pulled high, do not allow it to float. Always tie EA# to VCC if it is not connected to an external device.

6.The values in this column are valid until your software writes to Px_MODE.

A-8

Image 116

Intel 8XC196Jx, 8XC196Lx Table A-5 C196LA, LB Default Signal Conditions, Port Alternate During RESET# Upon RESET# Power

Contents

August Page Contents 8XC196LX Supplement Chapter Synchronous Serial I/O Port Entering and Exiting Once Mode Functional Groupings of Signals Default ConditionsProgramming the J1850 Controller Internal Timing Figures 11-3 Tables Guide to This Manual Page Manual Contents Chapter Guide to this Manual Related Documents Related Documents Architectural Overview Page Chapter Architectural Overview Microcontroller FeaturesFeatures of the 8XC196Lx and 8XC196Kx Product Famiies Block Diagram Internal Timing Clock Circuitry 87C196LA, LB Only State Times at Various Frequencies MHz12 MHz 16 MHz Multiplier State Time External TimingPllen CLK1 CLK0 Internal PeripheralsUprom Programming Values and Locations 1 I/O Ports Synchronous Serial I/O PortEvent Processor Array 4 J1850 Communications ControllerPage Address Space Page Address Map Chapter Address SpaceAddress Partitions Register File 1BFF JR, KR AddressCA,JT,KT USFR1 LA, LB Peripheral SPECIAL-FUNCTION RegistersXC196Lx Peripheral SFRs SSIO1CLK SSIO0CLKRstsrc Jdly Windowing Windows Upper Register File CA, JT, JV, KT, LA, LB BaseUpper Register File CA, JT, JV, KT 25H 0120H 49H 0100H 48H 24H 12H 4BH0140H Standard and PTS Interrupts Page Chapter Standard and PTS Interrupts Interrupt SOURCES, VECTORS, and Priorities Interrupt Controller PTS Service Interrupt RegistersInterrupt Sources, Vectors, and Priorities Interrupt Source Mnemonic Priority Name Interrupt Mask Registers IntmaskBit Function Number Bit Mnemonic Interrupt Description Interrupt Pending Registers INTMASK1LA, LD NMI Extint SSIO1 SSIO0 Interrupt Pending Intpend Register Intpend NMI Peripheral Transaction Server RegistersINTPEND1 Interrupt PTS Vector PtsselBit Interrupt Standard Vector PtssrvBits Ports Page Chapter Ports I/O Ports OverviewMicrocontroller Ports EPA, Ssio 8XC196LX Supplement Configuring Ports 1, 2, 5, and 6 Bidirectional Ports Ports 1, 2, 5, and 6 Internal Structure 87C196LA, LB Only For complementary output configurations Special Bidirectional Port Considerations Internal Structure for Ports 3 and 4 ADDRESS/DATA BUS 8XC196L X Supplement Synchronous Serial Port Page Chapter Synchronous Serial I/O Port Ssio 0 Clock RegisterBit Function For receptions Ssio 1 Clock Register 1FB7HCHS DUP Conint Conpnd Phas Pols CHS SSIO1CLK Page Event Processor Array Page Chapter Event Processor Array EPA Functional OverviewEPA Channels Device Capture/Compare Compare-only EPA Block Diagram 87C196LA, LB Only EPA Block Diagram 83C196LD Only EPAMASK1 EPA Mask RegistersEpamask EPAPEND1 EPA Pending RegistersEpapend Epaipv EPA Interrupt Priority Vector RegisterValue Interrupt J1850 Communications Controller Page PLL Clkout J1850 Communications ControllerJ1850 Functional Overview J1850 Communications Controller Block Diagram J1850 Controller Signals and Registers J1850 Controller SignalsSignal Control and Status Registers Cyclic Redundancy Check Generator J1850 Controller OperationControl State Machine Symbol Synchronization and Timing Circuitry Bus ContentionError Detection Bit Arbitration Delay Compensation Symbol Encoding and DecodingClock Prescaler Digital Filter Huntzicker Symbol Definition for J1850 Bit Arbitration Example Message Frames Bit Arbitration Example Standard Messaging HeaderCRC Byte Normalization Bit 64µS 128µS NB for IFR with CRC NB for IFR without CRC Huntzicker Symbol Timing Characteristics Name Symbol Bus Level TXmin TXnom TXmax RXmin RXmax Units In-frame Response Messaging IFR Messaging Type 1 Single Byte, Single Responder Transmitting and Receiving Messages Transmitting Messages Transmit Byte CPU JTX Jtxbuf CPU Jrxbuf Receiving MessagesReceive Byte Programming the J1850 Controller Programming the J1850 Command Jcmd RegisterIFR Messages Jcmd Auto IFR Ignore Abort MSG3 MSG2 MSG1 MSG0Auto MSG30 Operation Purpose Programming the J1850 Configuration Jcfg Register NBF IFR3 4XM Txbrk Rxpol PRE1 PRE0NBF IFR without CRC Byte Programming the J1850 Delay Compensation Jdly Register PRE1 PRE0 18. J1850 Delay Jdly Register Programming the J1850 Status Jstat Register Jstat Msgtx Msgrx Minimum Hardware Considerations Page Identifying the Reset Source Minimum Hardware Considerations Design Considerations for 8XC196LA, LB, and LD Special Operating Modes Page Chapter Special Operating Modes Entering and Exiting Once Mode 10-3 Page Programming Nonvolatile Memory Page Programming the Nonvolatile Memory Signature Word and Programming Voltage ValuesOtprom Address MAP Signature Word and Programming Voltage Values Slave Programming Circuit and Address MAP C196LA, LB Otprom Address MapAddress Range Description Hex CCB1 Description Address Comments Serial Port Programming Circuit and Address MAP Serial Port Programming Circuit Serial Port Programming Mode Address Map Description Address RangeA000-FFFFH Do not addressPage Signal Descriptions Page Appendix a Signal Descriptions Functional Groupings of Signals Table A-1 C196LA Signals Arranged by Functional Categories Signal Descriptions Table A-2 C196LB Signals Arranged by Functional Categories Figure A-2 C196LB 52-pin Plcc Package Table A-3 C196LD Signals Arranged by Functional Categories Input Name PinInput/Output Cont’d Name Pin Bus Control & Status Default Conditions Signals Functions Table A-5 C196LA, LB Default Signal ConditionsPort Alternate During RESET# Upon RESET# Power Table A-6 C196LD Default Signal Conditions Page Glossary Page BIT GlossaryALU Byte ESD DOUBLE-WORDEPA FET Integer ISR LONG-INTEGERLSB LSW MSB MSW PIC PIH PLL Ptscb PSWPTS QUAD-WORD Ralu SHORT-INTEGER SARSFR Uart Word VPWWDT Index Page Index Clkout Index-2