Intel 8XC196Lx, 8XC196Jx, 8XC196Kx, 87C196CA Interrupt Mask Registers, Intmask, Bit Function Number

STANDARD AND PTS INTERRUPTS

4.2.1Interrupt Mask Registers

Figures 4-1 and 4-2 illustrate the interrupt mask registers for the 8XC196Lx microcontrollers.

INT_MASK	Address:	0008H
	Reset State:	00H

The interrupt mask (INT_MASK) register enables or disables (masks) individual interrupt requests. (The EI and DI instructions enable and disable servicing of all maskable interrupts.) INT_MASK is the low byte of the processor status word (PSW). PUSHF or PUSHA saves the contents of this register onto the stack and then clears this register. Interrupt calls cannot occur immediately following a push instruction. POPF or POPA restores it.

		7								0
LA		—	—		AD	EPA0	EPA1	EPA2	EPA3	EPAx
		7								0
LB
		J1850RX	J1850TX		AD	EPA0	EPA1	EPA2	EPA3	EPAx
		7								0
LD
		—	—		—	EPA0	EPA1	EPA2	EPA3	EPAx
Bit						Function
Number
7:0†	Setting a bit enables the corresponding interrupt.
		Bit Mnemonic		Interrupt Description
		J1850RX		J1850 Receive (LB only)
		J1850TX		J1850 Transmit (LB only)
		AD		A/D Conversion Complete (LA, LB)
		EPA0		EPA Capture/Compare Channel 0
		EPA1		EPA Capture/Compare Channel 1
		EPA2		EPA Capture/Compare Channel 2
		EPA3		EPA Capture/Compare Channel 3
		EPAx††		Shared EPA interrupt
	††	EPA 6–9 capture/compare channel events, EPA 0–1 compare channel events†††								, EPA
		0–3 and 8–9 capture/compare overruns, and timer overflows can generate this
		multiplexed interrupt. The EPA mask and pending registers decode the EPAx interrupt.
		Write the EPA mask registers to enable the interrupt sources; read the EPA pending
		registers to determine which source caused the interrupt.
	†††	87C196LA, LB only.

†Bits 6–7 are reserved on the 87C196LA, and bits 5–7 are reserved on the 83C196LD. For compatibility with future devices, write zeros to these bits.

Figure 4-1. Interrupt Mask (INT_MASK) Register

4-3