LAN91C111

10/100 Non-PCI

Ethernet Single Chip

MAC + PHY

PRODUCT FEATURES

Datasheet

„Single Chip Ethernet Controller

„Dual Speed - 10/100 Mbps

„Fully Supports Full Duplex Switched Ethernet

„Supports Burst Data Transfer

„8 Kbytes Internal Memory for Receive and Transmit FIFO Buffers

„Enhanced Power Management Features

„Optional Configuration via Serial EEPROM Interface

„Supports 8, 16 and 32 Bit CPU Accesses

„Internal 32 Bit Wide Data Path (Into Packet Buffer Memory)

„3.3V MII (Media Independent Interface) MAC-PHY Interface Running at Nibble Rate

„MII Management Serial Interface

„128-Pin QFP package; lead-free RoHS compliant package also available.

„128-Pin TQFP package, 1.0 mm height; lead-free RoHS compliant package also available.

„Commercial Temperature Range from 0°C to 70°C (LAN91C111)

„Industrial Temperature Range from -40°C to 85°C (LAN91C111i)

„Built-in Transparent Arbitration for Slave Sequential Access Architecture

„Flat MMU Architecture with Symmetric Transmit and Receive Structures and Queues

„3.3V Operation with 5V Tolerant IO Buffers (See Pin List Description for Additional Details)

„Single 25 MHz Reference Clock for Both PHY and

MAC

„External 25Mhz-output pin for an external PHY supporting PHYs physical media.

„Low Power CMOS Design

„Supports Multiple Embedded Processor Host Interfaces

—ARM

—SH

—Power PC

—Coldfire

—680X0, 683XX

—MIPS R3000

Network Interface

„Fully Integrated IEEE 802.3/802.3u-100Base-TX/ 10Base-T Physical Layer

„Auto Negotiation: 10/100, Full / Half Duplex

„On Chip Wave Shaping - No External Filters Required

„Adaptive Equalizer

„Baseline Wander Correction

„LED Outputs (User selectable – Up to 2 LED functions at one time)

—Link

—Activity

—Full Duplex

—10/100

—Transmit

—Receive

SMSC LAN91C111 REV C

DATASHEET

Revision 1.91 (08-18-08)