SMSC LAN91C111 manual 16

					10/100 Non-PCI Ethernet Single Chip MAC + PHY
						Datasheet
PIN NO.		NAME	SYMBOL	BUFFER		DESCRIPTION
				TYPE
TQFP	QFP
42	44	Local Bus Clock	LCLK	I**		Input. Used to interface synchronous
						buses. Maximum frequency is 50 MHz.
						Limited to 8.33 MHz for EISA DMA burst
						mode. This pin should be tied high if it is
						in asynchronous mode.
38	40	Asynchronous	ARDY	OD16		Open drain output. ARDY may be used
		Ready				when interfacing asynchronous buses to
						extend accesses. Its rising (access
						completion) edge is controlled by the
						XTAL1 clock and, therefore,
						asynchronous to the host CPU or bus
						clock. ARDY is negated during
						Asynchronous cycle when one of the
						following conditions occurs:
						No_Wait Bit in the Configuration Register
						is cleared.
						Read FIFO contains less than 4 bytes
						when read.
						Write FIFO is full when write.
43	45	nSynchronous	nSRDY	O16		Output. This output is used when
		Ready				interfacing synchronous buses and
						nVLBUS=0 to extend accesses. This
						signal remains normally inactive, and its
						falling edge indicates completion. This
						signal is synchronous to the bus clock
						LCLK.
46	48	nReady Return	nRDYRTN	I**		Input. This input is used to complete
						synchronous read cycles. In EISA burst
						mode it is sampled on falling LCLK
						edges, and synchronous cycles are
						delayed until it is sampled high.
29	31	Interrupt	INTR0	O24		Interrupt Output – Active High, it’s used to
						interrupt the Host on a status event.
						Note: The selection bits used to
						determined by the value of INT SEL 1-0
						bits in the Configuration Register are no
						longer required and have been set to
						reserved in this revision of the FEAST
						family of devices.
45	47	nLocal Device	nLDEV	O16		Output. This active low output is asserted
						when AEN is low and A4-A15 decode to
						the LAN91C111 address programmed
						into the high byte of the Base Address
						Register. nLDEV is a combinatorial
						decode of unlatched address and AEN
						signals.
31	33	nRead Strobe	nRD	IS**		Input. Used in asynchronous bus
						interfaces.
32	34	nWrite Strobe	nWR	IS**		Input. Used in asynchronous bus
						interfaces.
34	36	nData Path	nDATACS	I with		Input. When nDATACS is low, the Data
		Chip Select		pullup**		Path can be accessed regardless of the
						values of AEN, A1-A15 and the content of
						the BANK SELECT Register. nDATACS
						provides an interface for bursting to and
						from the LAN91C111 32 bits at a time.
Revision 1.91 (08-18-08)			16			SMSC LAN91C111 REV C

DATASHEET