10/100 Non-PCI Ethernet Single Chip MAC + PHY

Datasheet

 

TXEMPTY INTR

 

 

Write Acknowledge Reg. with

 

 

TXEMPTY Bit Set

 

 

 

 

 

 

Read TXEMPTY & TX INTR

 

 

 

 

 

 

 

 

 

TXEMPTY = 0

TXEMPTY = X

TXEMPTY = 1

&

&

&

TXINT = 0

TXINT = 0

TXINT = 1

(Everything went through

(Waiting for Completion)

(Transmission Failed)

successfully)

 

 

 

Read Pkt. # Register & Save

Write Address Pointer

Register

Read Status Word from RAM

Update Statistics

Issue "Release" Command

 

Update Variables

 

 

 

Acknowledge TXINTR

Re-Enable TXENA

Restore Packet Number

Return to ISR

Figure 10.4 TXEMPTY INTR (Assumes Auto Release Option Selected)

SMSC LAN91C111 REV C

91

Revision 1.91 (08-18-08)

DATASHEET