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Datasheet
8.25 Bank 3 - RCV Register
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| C | RCV REGISTER |
| READ/WRITE |
| RCV |
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HIGH |
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BYTE |
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| 0 |
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| 0 |
| 0 | 0 |
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LOW | RCV |
| Reserved |
| Reserved |
| MBO | MBO |
| MBO |
| MBO | MBO |
BYTE | DISCRD |
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| 0 |
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| 1 | 1 |
| 1 |
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RCV DISCRD - Set to discard a packet being received. Will discard packets only in the process of being received. When set prior to the end of receive packet, bit 4 (RXOVRN) of the interrupt status register will be set to indicate that the packet was discarded. Otherwise, the packet will be received normally and bit 0 set (RCVINT) in the interrupt status register. RCV DISCRD is self clearing.
MBO - Must be 1.
8.26Bank 7 - External Registers
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0 |
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| THROUG |
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| H 7 | EXTERNAL REGISTERS |
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| nCSOUT is driven low by the LAN91C111 when a valid access to the EXTERNAL REGISTER range | |||||||||
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HIGH |
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| EXTERNAL R/W REGISTER |
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LOW |
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| EXTERNAL R/W REGISTER |
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Revision 1.91 | 68 | SMSC LAN91C111 REV C |
DATASHEET