10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
R/LT bits are also interrupt bits if they are not masked out with the Mask register bits. Interrupt bits automatically latch themselves into their register locations and assert the interrupt indication when they change state. Interrupt bits stay latched until they are read. When interrupt bits are read, the interrupt indication is deasserted and the interrupt bits that caused the interrupt to happen are updated to their current value. Each interrupt bit can be individually masked and subsequently be removed as an interrupt bit by setting the appropriate mask register bits in the Mask register.
lnterrupt indication is done in two ways: (1) MDINT bit in Interrupt Status Register, (2) INT bit in the PHY Ml Serial Port Status Output register. The INT bit is an active high interrupt register bit that resides in the PHY MI Serial Port Status Output register.
7.8Reset
The chip (MAC & PHY) performs an internal system reset when either (1) the RESET pin is asserted high for at least 100ns, (2) writing “1” to the SOFT_RST bit in the Receive Control Register, this reset bit is not a self-clearing bit, reset can be terminated by writing the bit low. It programs all registers to their default value. When reset is initiated by (1) and the EEPROM is presented and enabled, the controller will load the EEPROM to obtain the following configurations: 1) Configuration Register, 2) BASE Register, or/and 3) MAC Address. The internal MAC is not a power on reset device, thus reset is required after power up to ensure all register bits are in default state.
The internal PHY is reset when either (1) VDD is applied to the device, (2) the RST bit is set in the PHY Ml serial port Control register, this reset bit is a self-clearing bit, and the PHY will return a “1” on reads to this bit until the reset is completed, 3) the RESET pin is asserted high, (4) the SOFT_RST bit is set high and then cleared. When reset is initiated by (1) or (2), an internal power-on reset pulse is generated which resets all internal circuits, forces the PHY Ml serial port bits to their default values, and latches in new values for the MI address. After the power-on reset pulse has finished, the reset bit in the PHY Ml serial port Control registers cleared and the device is ready for normal operation. When reset is initiated by (3), the same procedure occurs except the device stays in the reset state as long as the RESET pin is held high. The internal PHY is guaranteed to be ready for normal operation 50 mS after the reset pin was de-asserted or the reset bit is set. Software driver requires to wait for 50mS after setting the RST bit to high to access the internal PHY again.
Revision 1.91 (08-18-08) | 42 | SMSC LAN91C111 REV C |