10/100 Non-PCI Ethernet Single Chip MAC + PHY

Datasheet

Asynchronous Cycle - nADS=0

 

t2

nDATACS

 

t3A

t4

Read Data

valid

 

t6A

t1A

t5

nRD,nWR

 

 

t5A

Write Data

D0~D31 valid

Figure 14.3 Asynchronous Cycle - nADS=0

 

PARAMETER

MIN

TYP

MAX

UNITS

 

 

 

 

 

 

t1A

nDATACS Setup to nRD, nWR Active

2

 

 

ns

 

 

 

 

 

 

t2

nDATACS Hold After nRD, nWR Inactive (Assuming nADS Tied

5

 

 

ns

 

Low)

 

 

 

 

 

 

 

 

 

 

t3A

nRD Low to Valid Data

 

 

30

ns

 

 

 

 

 

 

t4

nRD High to Data Invalid

2

 

15

ns

 

 

 

 

 

 

t5

Data Setup to nWR Inactive

10

 

 

ns

 

 

 

 

 

 

t5A

Data Hold After nWR Inactive

5

 

 

ns

 

 

 

 

 

 

t6A

nRD Strobe Width

30

 

 

ns

 

 

 

 

 

 

Address, AEN, nBE[3:0]

Valid Address

 

nRD, nWR

 

 

 

t26

t13

ARDY

t26A

 

 

Data

 

Valid

Valid Address

Valid Data

Figure 14.4 Asynchronous Ready

Revision 1.91 (08-18-08)

112

SMSC LAN91C111 REV C

DATASHEET